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2004

Scalability and Complexity of 2-Dimensional SIMD Extensions

XV Jornadas de Paralelismo

M. Álvarez, F. Sánchez, E. Salami, A. Ramirez, and M. Valero
Selecting Where to Simulate SPEC2000 Using Streams Analysis

XV Jornadas de Paralelismo

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
Stream Predictor Guided Instruction Decoding

XV Jornadas de Paralelismo

O. J. Santana, A. Falcón, A. Ramirez, and M. Valero
Throughput versus Quality of Service in SMT processors

Euromicro-DSD (Digital System Design)

E. Fernández, F. Cazorla, A. Ramirez, P. Knijnenburg, R. Sakellariou, and M. Valero

2003

Tolerating branch predictor latency on SMT

5th International Symposium on High Performance Computing (ISHPC-V)

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
An Analysis of Dynamic Instruction Streams

XIV Jornadas de Paralelismo

O. J. Santana, M. Galluzzi, A. Ramirez, and M. Valero
Latency Tolerant Branch Predictors

2003 International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA'03)

O. J. Santana, A. Ramirez, and M. Valero
Improving Memory Latency Aware Fetch Policies for SMT Processors

5th International Symposium on High Performance Computing (ISHPC-V)

F. Cazorla, E. Fernández, A. Ramirez, and M. Valero
CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era

Workshop on Complexity-Effective Design (WCED 2003)

C. Acosta, S. Vajapeyam, A. Ramirez, and M. Valero
Dealing with Billions of Transistors

XIV Jornadas de Paralelismo

C. Acosta, M. Galluzzi, S. Vajapeyam, A. Ramirez, and M. Valero

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