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2009

Thread to Core Assignment in SMT On-Chip Multiprocessors

21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero

2008

MFLUSH: Handling Long-latency loads in SMT On-Chip Multiprocessors.

International Conference on Parallel Processing (ICPP)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero

2007

Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors

1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero

2005

Complexity-Effectiveness in Multithreading Architectures

In 2005 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-2005)

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture

XVI Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
A Complexity-Effective Simultaneous Multithreading Architecture

34th International Conference on Parallel Processing (ICPP 2005)

C. Acosta, A. Falcón, A. Ramirez, and M. Valero

2004

Introducing Kilo-instruction Multiprocessors

XV Jornadas de Paralelismo

M. Galluzzi, V. Puente, O. J. Santana, C. Acosta, A. Cristal, R. Beivide, J. A. G. Monasterio, and M. Valero
Heterogeneity-Aware Architectures

XV Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero

2003

CDE: A Compiler-driven, Dependence-Centric, Eager-executing Architecture for the Billion Transistors Era

Workshop on Complexity-Effective Design (WCED 2003)

C. Acosta, S. Vajapeyam, A. Ramirez, and M. Valero
Dealing with Billions of Transistors

XIV Jornadas de Paralelismo

C. Acosta, M. Galluzzi, S. Vajapeyam, A. Ramirez, and M. Valero