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2007

Performance Impact of the Interconnection Network on MareNostrum Applications

1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007)

A. Ramirez, O. Prat, J. Labarta, and M. Valero
Performance Impact of Unaligned memory Operations in SIMD Extensions for Video CODEC Applications

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2007)

M. Álvarez, E. Salami, J. Labarta, and M. Valero

2006

Chip Multiprocessors with Implicit Transactions

2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06)

E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. E. Smith, and M. Valero
Boosting ILP{&}TLP with the Flexible Multi-Core (FMC)

2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06)

M. Pericas, A. Cristal, R. González, F. Cazorla, D. A. Jiménez, and M. Valero
Kilo-Instruction Processors, RunAhead and Prefetch

ACM International Conference on Computing Frontiers (CF 2006)

T. Ramírez, A. Cristal, O. J. Santana, A. Pajuelo, and M. Valero
A decoupled KILO-instruction processor

The 12th International Symposium on High-Performance Computer Architecture (HPCA-12)

M. Pericas, A. Cristal, R. González, D. Jiménez, and M. Valero
Reducing Simulation Time

2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06)

M. Moreto, A. Ramirez, and M. Valero
Kilo-instruction Processors: Overcoming the Memory Wall

M. Valero
A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures

J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero
Kilo-instruction Processors, Runahead and Prefetching

T. Ramírez, M. Pajuelo, O. J. Santana, and M. Valero

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