Mateo Valero Cortes

2004

• A Complexity-Effective Decoding Architecture Based on Instruction Streams

  Workshop on Complexity-Effective Design (WCED)

  O. J. Santana, A. Falcón, A. Ramirez, and M. Valero
• Implicit vs. Explicit Resource Allocation in SMT Processors

  2004 Euromicro Symposium on Digital Systems Design (DSD 2004)

  F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero

2003

• Ephemeral Registers with Multicheckpointing

  A. Cristal, J. F. Martínez, J. Llosa, and M. Valero
• Content Aware Register File Organisation

  R. González, A. Cristal, D. Ortega, and M. Valero
• A Case for Resource-conscious Out-of-order Processors

  A. Cristal, J. F. Martínez, J. Llosa, and M. Valero
• Out-of-Order Commit Processors

  A. Cristal, J. F. Martínez, D. Ortega, J. Llosa, and M. Valero
• A Simple Low-Energy Instruction Wakeup Mechanism

  5th International Symposium on High Performance Computing (ISHPC-V)

  M. A. Ramírez, A. Cristal, A. Veidenbaum, L. A. Villa, and M. Valero
• Kilo-instruction Processors

  5th International Symposium on High Performance Computing (ISHPC-V)

  A. Cristal, D. Ortega, J. Llosa, and M. Valero
• A Case for Resource Conscious Out-of-Order Processor

  MEDEA Workshop MEmory performance: DEaling with Applications , systems and architecture (MEDEA 2003)

  A. Cristal, J. F. Martínez, J. Llosa, and M. Valero
• A Low-Power-Instruction-Queue Wakeup Mechanism

  XIV Jornadas de Paralelismo

  M. A. Ramírez, A. Cristal, A. Veidenbaum, L. A. Villa, and M. Valero