Mateo Valero Cortes

2004

• Throughput versus Quality of Service in SMT processors

  Euromicro-DSD (Digital System Design)

  E. Fernández, F. Cazorla, A. Ramirez, P. Knijnenburg, R. Sakellariou, and M. Valero
• Speculative Execution for Hiding Memory Latency

  A. Pajuelo, A. González, and M. Valero
• High Performance and Low Power VLIW for Numerical Applications

  M. Pericas, E. Ayguade, J. Zalamea, J. Llosa, and M. Valero
• Dynamic Memory Instruction Bypassing

  D. Ortega, M. Valero, and E. Ayguade
• Late Allocation and Early Release of Physical Registers

  T. Monreal, V. Viñals, J. González, A. González, and M. Valero
• Software and Hardware Techniques to Optimize Register File Utilization in VLIW

  J. Zalamea, J. Llosa, E. Ayguade, and M. Valero
• Register-constrained Modulo Scheduling

  J. Zalamea, J. Llosa, E. Ayguade, and M. Valero
• Initial Evaluation of Multimedia Extensions on VLIW Architectures

  E. Salami, and M. Valero
• Performance and Power Evaluation of Clustered VLIW Processors with Functional Units

  M. Pericas, E. Ayguade, J. Zalamea, J. Llosa, and M. Valero
• Prophet/Critic Hybrid Branch Prediction

  31st Annual International Symposium on Computer Architecture (ISCA-31)

  A. Falcón, J. Stark, A. Ramirez, K. Lai, and M. Valero