Mateo Valero Cortes

2004

• Heterogeneity-Aware Architectures

  XV Jornadas de Paralelismo

  C. Acosta, A. Falcón, A. Ramirez, and M. Valero
• A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors

  ACM Transactions on Architecture and Code Optimization

  O. J. Santana, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
• Traffic Aggregation Impact on the Memory Performance of Networking Applications

  J. Verdú, M. Nemirovsky, J. García, and M. Valero
• Analysis of Traffic Traces for Stateful Applications

  J. Verdú, J. García, M. Nemirovsky, and M. Valero
• Limits on Early Release of Physical Registers

  J. J. Alastruey, T. Monreal, V. Viñals, and M. Valero
• Aggressive Speculative Execution for Hidding Memory Latency

  A. Pajuelo, A. González, and M. Valero
• Scalability and Complexity of 2-Dimensional SIMD Extensions

  XV Jornadas de Paralelismo

  M. Álvarez, F. Sánchez, E. Salami, A. Ramirez, and M. Valero
• Analysis of Traffic Traces for Statefull Applications

  J. Verdú, J. García, M. Nemirovsky, and M. Valero
• Selecting Where to Simulate SPEC2000 Using Streams Analysis

  XV Jornadas de Paralelismo

  A. Falcón, O. J. Santana, A. Ramirez, and M. Valero
• Stream Predictor Guided Instruction Decoding

  XV Jornadas de Paralelismo

  O. J. Santana, A. Falcón, A. Ramirez, and M. Valero