Mateo Valero Cortes

2006

• Performance Analysis of Sequence Alignment Applications

  IISWC, IEEE Internacional Symposium on Workload Characterization

  F. Sánchez, E. Salami, A. Ramirez, and M. Valero
• Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors

  T. Morad, U. Weiser, A. Kolodny, M. Valero, and E. Ayguade
• A DRAM/SRAM Memory Scheme for Fast Packet Buffers

  J. Vidal, M. March, L.. Cerdá, J. Corbal, and M. Valero
• Predictable Performance in SMT processors: Synergy Between the OS and SMTs

  IEEE Transactions on Computers

  F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
• Analysis of Simultaneous Multithreading Implementations in Current High-Performance Processors

  K. Kedzierski, F. Cazorla, and M. Valero
• A First Glance at the Implementation of Precise Recoveries in Out-of-order Commit Processors

  I. González, O. J. Santana, A. Pajuelo, and M. Valero
• Looking for novel ways to obtain fair measurements in multithreaded architectures

  J. Vera, F. Cazorla, A. Pajuelo, O. J. Santana, E. Fernández, and M. Valero
• Analysis of multithreading capabilities of current high-performance processors

  K. Kedzierski, F. Cazorla, and M. Valero
• Improving EDF for SMT processors

  C. Boneti, F. Cazorla, and M. Valero
• Implementando recuperaciones precisas en procesadores con consolidación fuera de orden

  I. González, O. J. Santana, A. Pajuelo, and M. Valero