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2014

DaSH: A Benchmark for Hybrid Dataflow and Shared Memory Programming Models

ACM International Conference on Computing Frontiers

V. Gajinov, I. Eric, S. Stipic, O. Unsal, E. Ayguade, and A. Cristal
EVX: Vector Execution on Low Power EDGE Cores

ACM/IEEE Design, Automation, and Test in Europe 2014

M. Duric, O. Palomar, A. Smith, O. Unsal, A. Cristal, M. Valero, and D. Burger
Dynamic-Vector Execution on a General Purpose EDGE Chip Multiprocessor

14th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2014)

M. Duric, O. Palomar, A. Smith, Milan Stanic, O. Unsal, A. Cristal, and M. Valero
Neighbor-cell assisted error correction for MLC NAND flash memories

SIGMETRICS

Y. Cai, G. Yalcin, O. Mutlu, E. Haratsch, O. Unsal, A. Cristal, and K. Mai
PVMC: Programmable Vector Memory Controller

IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2014)

T. Hussain, O. Palomar, O. Unsal, A. Cristal, E. Ayguade, and M. Valero
Advanced Pattern based Memory Controller for FPGA based HPC Applications

International Conference on High Performance Computing {&} Simulation, HPCS 2014

T. Hussain, O. Palomar, O. Unsal, A. Cristal, E. Ayguade, and M. Valero
MAPC. Memory Access Pattern based Controller

24th International Conference on Field Programmable Logic and Applications (FPL), 2014

T. Hussain, O. Palomar, O. Unsal, A. Cristal, E. Ayguade, and M. Valero
Analyzing performance improvements and energy savings in Infiniband Architecture using network compression

International Symposium on Computer Architecture and High Performance Computing

B. Dickov, M. Pericas, P. Carpenter, N. Navarro, and E. Ayguade
EUROSERVER: Energy Efficient Node for European Micro-servers

17th Euromicro Conference on Digital System Design

Y. Durand, P. Carpenter, S. Adami, A. Bilas, J. Duato, A. Farcy, G. Gaydadjiev, J. Goodacre, M. Katevenis, M. Marazakis, E. Matus, and I. Mavroidis
Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors

Third International Workshop On-chip memory hierarchies and interconnects: organization, management and implementation

V. Garcia, A. Rico, C. Villavieja, P. Carpenter, N. Navarro, and A. Ramirez

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