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2011

A Flexible Hybrid Transactional Memory Multicore on FPGA

Jornadas de Paralelismo 2011

O. Arcas, N. Sönmez, O. Unsal, A. Cristal, and M. Valero
DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory

Parallel Architectures and Compilation Techniques (PACT)

C. Villavieja, V. Karakostas, L. Vilanova, Y. Etsion, A. Ramirez, A. Mendelson, N. Navarro, A. Cristal, and O. Unsal
Interchangeable Back Ends for STM Compilers

6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT)

G. Kestor, L. Dalessandro, A. Cristal, M. L. Scott, and O. Unsal
Object Oriented execution Model (OOM)

New Directions in Computer Architecture (NDCA-2)

N. Markovic, D. Nemirovsky, R. González, O. Unsal, M. Valero, and A. Cristal
A Comprehensive Study of Conflict Resolution Policies in Hardware Transactional Memory

6th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT)

E. Akpinar, S. Tomić, A. Cristal, O. Unsal, and M. Valero
Circuit Design of a Dual-Versioning L1 Data Cache for Optimistic Concurrency

21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11)

A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero
Integrating Dataflow Abstractions into Transactional Memory

First Workshop on Systems for Future Multi-Core Architectures (SFMA'11)

V. Gajinov, M. Milovanovic, O. Unsal, A. Cristal, E. Ayguade, and M. Valero
RMS-TM: A Comprehensive Benchmark Suite for Transactional Memory Systems

International Conference on Performance Engineering (ICPE 2011)

G. Kestor, V. Karakostas, O. Unsal, A. Cristal, I. Hur, and M. Valero
From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype

The 7th International Symposium on Applied Reconfigurable Computing (ARC 2011)

N. Sönmez, O. Arcas, G. Sayilar, A. Cristal, I. Hur, O. Unsal, S. Singh, and M. Valero
Circuit Design of a Dual-Versioning L1 Data Cache

Integration The VLSI Journal

A. Seyedi, A. Armejach, A. Cristal, O. Unsal, I. Hur, and M. Valero

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