Publications

Export results as:

Showing 4161 - 4170 results of 5686

2011

Reconfigurable Memory Controller with Programmable Pattern Support

5th HiPEAC Workshop on Reconfigurable Computing (WRC 2011)

T. Hussain, M. Pericas, and E. Ayguade
A Template System for the Efficient Compilation of Domain Abstractions onto Reconfigurable Computers

5th HiPEAC Workshop on Reconfigurable Computing (WRC 2011)

M. Shafiq, M. Pericas, and E. Ayguade
TARCAD: A template architecture for reconfigurable accelerator designs

IEEE Symposium on Application Specific Processors (SASP)

M. Shafiq, M. Pericas, N. Navarro, and E. Ayguade
A parallel finite-element method for 3-D marine controlled-source electromagnetic forward modeling

Global Meeting Abstracts

J. Koldan, V. Puzyrev, J M.. Cela, J. de la Puente, and F. Ortigosa
True Vector Extensions for Decision Support DBMS Acceleration

T. Hayes, O. Palomar, O. Unsal, A. Cristal, and M. Valero
FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware

Workshop on Wild and Sane Ideas in Speculation and Transactions

G. Yalcin, O. Unsal, A. Cristal, and M. Valero
FIMSIM: A fault injection infrastructure for microarchitectural simulators

29th International Conference on Computer Design (ICCD)

G. Yalcin, O. Unsal, A. Cristal, and M. Valero
SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory

Parallel Architectures and Compilation Techniques (PACT)

G. Yalcin, O. Unsal, A. Cristal, I. Hur, and M. Valero
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory

Parallel Architectures and Compilation Techniques (PACT)

A. Armejach, A. Seyedi, R T. J. Gil, I. Hur, O. Unsal, A. Cristal, and M. Valero
Rapid Development of Error-Free Architectural Simulators using Dynamic Runtime Testing

23rd International Symposium on Computer Architecture and High Performance Computing

S. Tomić, A. Cristal, O. Unsal, and M. Valero

Pages