Publications

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2001

Code Layout Optimizations for Transaction Processing Workloads

28th Annual International Symposium on Computer Architecture (ISCA-28)

A. Ramirez, L. A. Barroso, K. Gharachorloo, R. Cohn, J. Lluis Larriba-Pey, G. Lowney, and M. Valero
Instruction Fetch Architectures and Code Layout Optimizations

Proceedings of the IEEE

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
An In-Depth Evaluation of the Multi-Stage Cascaded Predictor

XII Jornadas de Paralelismo, Valencia (Spain)

O. J. Santana, A. Falcón, E. Fernández, P. Medina, A. Ramirez, and M. Valero
An Analysis of Dynamic History Length Fitting

XII Jornadas de Paralelismo, Valencia (Spain)

A. Falcón, O. J. Santana, P. Medina, E. Fernández, A. Ramirez, and M. Valero
Branch Prediction Using Profile Data

7th International Euro-Par Conference (Euro-Par'2001)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Efficient Execution of Parallel Java Applications

3rd Annual Workshop on Java for High Performance Computing

J. Guitart, X. Martorell, J. Torres, and E. Ayguade
Performance Analysis of Parallel Java Applications on Shared-memory Systems

30th International Conference on Parallel Processing (ICPP'01)

J. Guitart, J. Torres, E. Ayguade, and M. Bull
Strategies for Efficient Exploitation of Loop-Level Parallelism in Java Concurrency and Computation

Concurrency and Computation: Practice and Experience

J. Oliver, J. Guitart, E. Ayguade, N. Navarro, and J. Torres

2000

A Stream Processor Front-end

IEEE Technical Committee on Computer Architecture Newsletter

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
The Effect of Code Reordering on Branch Prediction

International Conference on Parallel Architectures and Compilation Techniques (PACT 2000)

A. Ramirez, J. Lluis Larriba-Pey, and M. Valero

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