15th International Workshop on Worst-Case Execution Time Analysis (WCET 2015). Lund, Sweden. 7th July.

The 15th International Workshop on Worst-Case Execution time Analysis (WCET 2015) is a satellite workshop of the 27th Euromicro Conference on Real-Time Systems (ECRTS 2015) , the premier European venue for presenting research into the broad area of real-time and embedded systems.

Date: 07/Jul/2015

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Important Dates

  • Submission Deadline: May 1st, 2015
  • Notification: 22nd May, 2015
  • Final Version Deadline: 9th June, 2015
  • Workshop: 7th July, 2015

(Common dates for all ECRTS satellite workshops)

15th International Workshop on WCET Analysis

The 15th International Workshop on Worst-Case Execution time Analysis (WCET 2015) is a satellite workshop of the 27th Euromicro Conference on Real-Time Systems (ECRTS 2015), the premier European venue for presenting research into the broad area of real-time and embedded systems. WCET 2015 is kindly sponsored by TACLe (www.tacle.eu), an European COST-Action on Timing Analysis on Code-Level, FP7 IP Project PROXIMA (www.proxima-project.eu). WCET 2015 is supported by the HiPEAC Network of Excellence (www.hipeac.net).


 WCET workshop is the reference forum for academics, practitioners and industrials in any aspect related to the timing analysis of computer systems. While in the past timing analysis has been a topic mainly for real-time systems, recently it has becoming crucial in other domains dealing with timing guarantees. This includes among other mobile computing and high-performance computing. This edition of the WCET workshop, besides papers targeting traditional WCET analysis, encourages submissions focused on less rigorous and mature timing analysis techniques on complex multicore and manycore heterogeneous, usually COTS, architectures. For such complex architectures Execution Time Bound (ETB) estimates are derived rather than WCET estimates in the strict sense.  ETB estimates are intrinsically less reliable than WCET estimates.


This workshop seeks original contributions on topics that include but are not limited to:

  • WCET/ETB analysis for multi- and many-core systems
  • WCET/ETB analysis for multi-threaded applications
  • WCET/ETB analysis for COTS processors
  • Case studies, and industrial experience of WCET/ETB analysis
  • Timing Analysis and safety standards
  • Different approaches to WCET/ETB computation
  • Probabilistic timing analysis
  • Tools for WCET/ETB analysis
  • Timing-predictable operating systems and processor designs
  • Compiler-based optimization of worst-case timing
  • Low-level timing analysis, modeling and analysis of processor features
  • Flow analysis for WCET, loop bounds, infeasible paths
  • Integration of timing analysis and schedulability analysis
  • Integration of timing  analysis in development processes
  • Methods and benchmarks for timing analysis evaluation

Innovative, controversial statements or that present new approaches are specially sought.


Call for Papers

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Online Proceedings now avaiable

Find them following this link

Program Chair

Francisco J. Cazorla , Barcelona Supercomputing Center and IIIA-CSIC, Spain

Program Committee

Benoît Triquet, Airbus
Björn Lisper,  Univ. College of Mälardalen
Christine Rochange, IRIT
Claire Maiza, Verimag
Damien Hardy, IRISA
Enrico Mezzetti, University of Padua
Franck Wartel, Airbus
Guillem Bernat, Rapita Systems
Heiko Falk, TU Hamburg-Harburg
Isabelle Puaut, IRISA
Jaume Abella, BSC
Luca Fossati, ESA
Luis Miguel Pinho, CISTER
Peter Puschner, TU Wien
Tullio Vardanega, University of Padua

Steering Committee

Guillem Bernat, Rapita Systems Ltd., UK Björn Lisper,  Univ. College of Mälardalen, SE Isabelle Puaut, IRISA Peter Puschner, TU Wien

Final Program

08:00 – 09:00 Registration opens
Session Chair Francisco J. Cazorla
09:00 – 09:05 Francisco J. Cazorla
Introduction to WCET 2015
09:05 – 09:30 Hugues Cassé, Haluk Ozaktas and Christine Rochange.
A Framework to Quantify the Overestimations of Static WCET Analysis
09:30 – 10:00 Marco Ziccardi, Alessandro Cornaglia, Enrico Mezzetti and Tullio Vardanega.
Software-enforced Interconnect Arbitration for COTS Multicores
10:00 – 10:30 Mahdi Eslamimehr and Hesam Samimi.
Timing Analysis of Event-Driven Programs with Directed Testing
10:30 – 11:00 BREAK
Session Chair Enrico Mezzetti
11:00 – 11:30 Peter Wägemann, Tobias Distler, Timo Hönig, Volkmar Sieh and Wolfgang Schröder-Preikschat.
GenE: A Benchmark Generator for WCET Analysis
11:30 – 12:00 Boris Dreyer, Christian Hochberger, Simon Wegener and Alexander Weiss.
Precise Continuous Non-Intrusive Measurement-Based Execution Time Estimation
12:00  - 12:30 Clément Ballabriga, Julien Forget and Giuseppe Lipari.
Context-sensitive parametric WCET analysis
12:30 – 13:30 BREAK
Session Chair Francisco J. Cazorla
13:30 – 14:00 Keynote by Jon Perez (Embedded Systems research line coordinator” at IK4-IKERLAN). "Multicore, WCET and IEC-61508 certification of fail-safe mixed-criticality systems"
14:00 – 14:30
14:30 – 15:00 Sebastian Altmeyer, Björn Lisper, Claire Maiza, Jan Reineke and Christine Rochange.
WCET and MC: What does Confidence in WCET Estimations Depend Upon?
15:00 – 15:30 BREAK
Session Chair Luis Miguel Pinho
15:30 – 16:00 Georg Wassen and Stefan Lankes.
Bare-Metal Execution of Hard Real-Time Tasks Within a General-Purpose Operating System
16:00 – 16:30 Niklas Holsti, Jan Gustafsson, Linus Källberg and Björn Lisper.
Analysing Switch-Case Code with Abstract Execution
16:30 – 17:00 Jordy Ruiz and Hugues Cassé.
Using SMT Solving for the Lookup of Infeasible Paths in Binary Programs
17:00 End of the Workshop


Keynote Speaker
Dr. Jon Pérez is the coordinator of the embedded systems research group at IK4-IKERLAN and works in the development and certification of safety-critical embedded systems. For example SIL4 railway signalling systems (ERTMS/ETCS), SIL3/Pld industrial machinery and wind-turbine protection systems. He has previously worked for Motorola Semiconductor in the field of multicore DSPs. He is a certified TÜV Rheinland Functional Safety engineer (Fs/Eng.2378 / 10) and member of the Spanish Committee AEN/CTN 200 (safety standards) at ISO International Organization for Standardization. Research interests focus on distributed real-time, mixed-criticality and safety-critical embedded systems. He collaborates among others in FP7 MULTIPARTES, FP7 DREAMS and FP7 PROXIMA research projects. He has received a B. Eng in Industrial and Robotics at Mondragon University, a M.Sc. in Electronics & Electrical Engineering with distinction at the University of Glasgow and he finished his doctoral studies in Computer Science at TU Wien in the field of safety-critical embedded systems.

Author Agreement

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Submission Portal


Submission Deadline: May 1st, 2015

Submission Instructions

Research papers should present original research results not published or submitted for publication in other forums. Accepted papers will be published via Schloss Dagstuhl's OASIcs online proceedings series, indexed, with ISBN. By submitting a paper, the authors agree and confirm that: neither this paper nor a version close to it is under submission or will be submitted elsewhere before notification by WCET 2015, and if accepted, at least one author will register for WCET 2015 by the special registration deadline set in the notification of acceptance, and present the paper at the workshop in person.

Papers submitted for the WCET workshop must be written in English, must not exceed 10 pages, should conform with the typesetting requirements specified below, and must be submitted in PDF format using the WCET workshop paper submission website. Author names, affiliations and self-references should not be anonymized.

Typesetting Requirements

Authors have to use a dedicated OASIcs LaTeX style to produce their submissions and final paper versions. The style file provides several features for authors:

  • titlepage environment,
  • abstract environment,
  • provision of ACM 1998 classification environment,
  • topical keywords.

The OASIcs LaTeX style templates are available at http://drops.dagstuhl.de/styles/oasics/oasics-authors.tgz.

These LaTeX style files for OASIcs require the usage of pdflatex. Please ensure that you have an up-to-date LaTeX environment available. The papers should be submitted by the authors using the oasics.cls LaTeX style available from http://drops.dagstuhl.de/styles/oasics/oasics-authors.tgz.

In order to improve the quality of the proceedings and to simplify the overall publication process, authors of submissions should follow the guidelines below:

  • Use pdflatex.
  • Use further LaTeX packages only if absolutely required.
  • Do not use a different main font. For example, usage of times-package is forbidden.
  • Provide full author names (especially with regard to the first name).
  • Fill out the \subjclass and \keywords macros. For the \subjclass, please refer to the ACM 1998 classification.
  • Take care of suitable linebreaks and pagebreaks. No overfull \hboxes should occur in the warnings log.
  • Provide suitable graphics of at least 300dpi (preferrably in pdf format).
  • Use the provided sectioning macros: \section, \subsection, \subsection*, \paragraph, ...
  • Keep the standard style (plain) for the bibliography as provided by the oasics.cls style file.
  • Use a spellchecker to get rid of typos.
  • For the abstract, only very simple LaTeX commands are allowed, e.g., $h_i$. LaTeX commands starting with a backslash "\" are not allowed. We suggest to avoid LaTeX commands in the abstract at all. In particular, the abstract must not contain complex LaTeX formulas or literature references. These rules are a prerequisite for a successful submission of accepted papers to indexing agencies like DBLP.
  • A manual for the LIPIcs style is available at http://drops.dagstuhl.de/styles/oasics/oasics-authors/oasics-manual.pdf.

All accepted articles are published under a Creative Commons Attribution 3.0 Unported license (CC-BY 3.0). Hereby, the authors retain their copyright. For each paper, the corresponding author has to sign an author agreement which clarifies the different roles within the publishing process.

Past Workshops

WCET Workshop 2014 - General Chair Heiko Falk

WCET Workshop 2013 - General Chair Claire Maiza

WCET Workshop 2012 - General Chair Tullio Vardanega

WCET Workshop 2011 - General Chris Healy

Sponsored by


TACLE - Timing Analysis on Code-Level


Supported by


Satellite Workshop of