Publications

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2007

Explaining Dynamic Cache Partitioning Speed Ups

IEEE Computer Architecture Letters

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Online Prediction of Applications Cache Utility

International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS)

M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
Core to Memory Interconnection Implications for Forthcoming On-Chip Multiprocessors

1st Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI 2007)

C. Acosta, F. Cazorla, A. Ramirez, and M. Valero
Performance Impact of the Interconnection Network on MareNostrum Applications

1st Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2007)

A. Ramirez, O. Prat, J. Labarta, and M. Valero
Performance Impact of Unaligned memory Operations in SIMD Extensions for Video CODEC Applications

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2007)

M. Álvarez, E. Salami, J. Labarta, and M. Valero
CellSim: A Validated Modular Heterogeneous Multiprocessor Simulator

XVIII Jornadas de Paralelismo de Zaragoza

F. Cabarcas, A. Rico, D. Ródenas, X. Martorell, A. Ramirez, and E. Ayguade
Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2007)

D. Jiménez-González, X. Martorell, and A. Ramirez
High Performance Embedded Architectures and Compilation Roadmap

K D. Bosschere, W. Luk, X. Martorell, N. Navarro, M. O'Boyle, D. Pnevmatikatos, A. Ramirez, P. Sainrat, A. Seznec, P. Stenström, and O. Temam
A Streaming Machine Description and Programming Model

7th Intl. Workshop on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS VII)

P. Carpenter, D. Ródenas, X. Martorell, A. Ramirez, and E. Ayguade
Implementation and Validation of a Cell Simulator using UNISIM

3rd HiPEAC Industrial Workshop

A. Rico, F. Cabarcas, D. Ródenas, X. Martorell, A. Ramirez, and E. Ayguade

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