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2013

APPLE: Adaptive Performance-Predictable Low-Energy Caches for Reliable Hybrid Voltage Operation

50th Annual Design Automation Conference (DAC)

B. Maric, J. Abella, and M. Valero
Measurement-Based Probabilistic Timing Analysis: Lessons from an Integrated-Modular Avionics Case Study

8th IEEE International Symposium on Industrial Embedded Systems (SIES)

F. Wartel, L. Kosmidis, C. Lo, B. Triquet, E. Quinones, J. Abella, A. Gogonel, A. Baldovin, E. Mezzetti, L. Cucu-Grosjean, T. Vardanega, and F. Cazorla
Deconstructing Bus Access Control Policies for Real-Time Multicores

8th IEEE International Symposium on Industrial Embedded Systems (SIES)

J. Jalle, J. Abella, E. Quinones, L. Fossati, M. Zulianello, and F. Cazorla
On the Convergence of Mainstream and Mission Critical Markets

50th Annual Design Automation Conference (DAC)

S. Girbal, M. Moreto, A. Grasset, J. Abella, E. Quinones, F. Cazorla, and S. Yehia
Probabilistic Timing Analysis on Conventional Cache Designs

ACM/IEEE Design, Automation, and Test in Europe (DATE)

L. Kosmidis, C. Curtsinger, E. Quinones, J. Abella, E. D. Berger, and F. Cazorla
A Cache Design for Probabilistically Analysable Real-Time Systems

ACM/IEEE Design, Automation, and Test in Europe (DATE)

L. Kosmidis, J. Abella, E. Quinones, and F. Cazorla
Circuit Design of a Novel Adaptable and Reliable L1 Data Cache

23rd ACM international conference on Great lakes symposium on VLSI

A. Seyedi, G. Yalcin, O. Unsal, and A. Cristal
Fault Tolerance for Multi-Threaded Applications by Leveraging Hardware Transactional Memory

10th conference on ACM Computing Frontiers

G. Yalcin, O. Unsal, and A. Cristal
On the Selection of Adder Unit in Energy Efficient Vector Processing

14th International Symposium on Quality Electronic Design (ISQED)

Ivan Ratkovic, O. Palomar, Milan Stanic, O. Unsal, A. Cristal, and M. Valero
FaulTM: Error Detection and Recovery Using Hardware Transactional Memory

ACM/IEEE Design, Automation, and Test in Europe (DATE)

G. Yalcin, O. Unsal, and A. Cristal

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