BSC researchers selected for two HiPEAC Tech Transfer Awards

22 December 2017

Two research teams at Barcelona Supercomputing Center (BSC) have been selected for a HiPEAC Tech Transfer Award 2017.

On behalf of the Computer Architecture – Operating Systems (CAOS) group in the Computer Science department, Francisco J. Cazorla won an award for the entry titled ‘Enabling Real-Time Guarantees on Multicores with Rapita’s Verification Suite and BSC's Micro-Benchmark Technology’. The award was for the partnership and framework agreement between BSC and Rapita Systems to provide consultancy services relating to multicore timing analysis. As part of the agreement, BSC and Rapita are currently integrating BSC’s multicore micro-benchmark technology, or MµBT, into Rapita Systems’ analysis tool RapiTime to offer industrial-quality worst-case execution time (WCET) estimates for critical real-time embedded systems (CRTES) to industry.

RapiTime allows clients in the automotive and avionics sectors to obtain evidence that critical functions – such as braking – will be performed within a certain time limit. With the rise of multicore processors in the automotive and avionics sectors, thanks in part to the advent of autonomous vehicles, there was a clear market for improving multicore processor timing analysis. The integration of BSC’s MµBT into Rapita’s RapiTime is a step towards an industry-ready suite of verification tools for multicore processors.

‘This is the way forward to bringing this technology into industrial domains, such as the automotive sector. We believe that our relationship with Rapita is fundamental in this respect,’ commented Cazorla, leader of the CAOS group at BSC.

The project came about thanks to work undertaken with Rapita during the PROXIMA (Probabilistic real-time control of mixed-criticality multicore and manycore systems) project, which received funding from the European Commission. This work is being also supported by the European Regional Development Fund (ERDF) of the European Union in the framework of the ERDF (FEDER) program in Catalonia 2014-2020 under the grant SDESI (2016PROD 00115).

A second Tech Transfer Award was obtained by the entry ‘OmpSs@FPGA for Industrial Internet of Things’, submitted by Carlos Álvarez on behalf of a team of BSC-UPC researches within the Computer Science department. Building on work undertaken by BSC-UPC staff over a period of years, this project involved the adaptation of BSC’s flagship programming model, OmpSs, for execution on field-programmable gate array (FPGA) processors in the context of the industrial internet of things (IoT).

‘An example of a simple use case in the industrial IoT would be a temperature sensor which ensures that a machine turns itself off before it overheats,’ commented Álvarez. ‘With increasingly sophisticated applications, such as artificial intelligence for smarter machines, more processors are required – which is where OmpSs comes in.’

OmpSs was originally developed by BSC Computer Sciences Director Jesús Labarta for use on high-performance computers, but is becoming increasingly relevant for embedded systems as they become more complex and also include non-traditional computing architectures.

‘The significance of this project is that it will help program the processors of the future,’ added Álvarez. ‘As a result, BSC will be able to influence how this area develops.’

The project is a collaboration with the Basque research, development and innovation (R+D+I) institution IKERGUNE. It builds on work undertaken by the team within the European Commission-funded AXIOM (Agile, eXtensible, fast I/O Module for the cyber-physical era) project.

About HiPEAC

Since 2004, the HiPEAC (High Performance and Embedded Architecture and Compilation) project has provided a hub for European researchers in computing systems; today, its network, the biggest of its kind in the world, numbers almost 2,000 specialists. The project offers training, mobility support and dissemination and recruitment services, along with numerous networking facilities to its members. The latest incarnation of the project, HiPEAC 5, began on 1 December 2017 and is delivered by 13 partners, led by Ghent University. It is a Coordination and Support Action funded by the European Union’s Horizon 2020 research and innovation programme under grant agreement no. 779656.