Computer Architecture - Operating Systems (CAOS)

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2016

pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems

2016 Euromicro Conference on Digital System Design (DSD)

M. Slijepcevic, M. Fernández, C. Hernández, J. Abella, E. Quiñones, and F. J. Cazorla
Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems

2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)

M. Panic, C. Hernández, E. Quiñones, J. Abella, and F. J. Cazorla
Fitting processor architectures for measurement-based probabilistic timing analysis

Microprocessors and Microsystems

L. Kosmidis, E. Quiñones, J. Abella, T. Vardanega, C. Hernández, A. Gianarro, I. Broster, and F. J. Cazorla
On the Analysis of the Timing Behaviour of Time Randomised Caches

P. Benedicte
Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore

ACM Trans. Embed. Comput. Syst.

T. Ungerer, C. Bradatsch, M. Frieb, F. Kluge, J. Mische, A. Stegmeier, R. Jahr, M. Gerdes, P. Zaykov, L. Matusova, Z. Jian Jia Li, Z. Petrov, B. Böddeker, S. Kehr, H. Regler, A. Hugl, C. Rochange, H. Ozaktas, H. Cassé, A. Bonenfant, P. Sainrat, N. Lay, D. George, I. Broster, E. Quinones, M. Panic, J. Abella, C. Hernández, F. Cazorla, S. Uhrig, M. Rohde, and A. Pyka
Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis

19th Euromicro Conference on Digital Systems Design (DSD)

F. Cazorla, J. Abella, J. Andersson, T. Vardanega, F. Vatrinet, I. Bate, I. Broster, M. Azkarate-askasua, F. Wartel, L. Cucu-Grosjean, F. Cros, G. Farrall, A. Gogonel, A. Gianarro, B. Triquet, C. Hernández, C. Lo, C. Maxim, D. Morales, E. Quinones, E. Mezzetti, L. Kosmidis, I. Agirre, M. Fernández, M. Slijepcevic, P. Ryan Conmy, and W. Talaboulma
TASA: Toolchain-Agnostic Static Software Randomisation for Critical Real-Time Systems

35th International Conference On Computer Aided Design (ICCAD)

L. Kosmidis, R. Vargas, D. Morales, E. Quinones, J. Abella, and F. Cazorla
Measurement-Based Timing Analysis of the AURIX Caches

16th International Workshop on Worst-Case Execution Time Analysis (WCET)

L. Kosmidis, D. Compagnin, D. Morales, E. Mezzetti, E. Quinones, J. Abella, T. Vardanega, and F. Cazorla
Modeling RTL Fault Models Behavior to Increase the Confidence on TSIM-based Fault Injection

22nd IEEE International On-Line Testing Symposium (IOLTS)

J. Espinosa, C. Hernández, and J. Abella
Random Modulo: a New Processor Cache Design for Real-Time Critical Systems

53rd Design Automation Conference (DAC)

C. Hernández, J. Abella, A. Gianarro, J. Andersson, and F. Cazorla
A Confidence Assessment of WCET Estimates for Software Time Randomized Caches

2016 IEEE 14th International Conference on Industrial Informatics (INDIN)

P. Benedicte, L. Kosmidis, E. Quinones, J. Abella, and F. Cazorla
Modelling the Confidence of Timing Analysis for Time Randomised Caches

2016 11th IEEE International Symposium on Industrial Embedded Systems (SIES)

P. Benedicte, L. Kosmidis, E. Quinones, J. Abella, and F. Cazorla
Resilient Random Modulo Cache Memories for Probabilistically-Analyzable Real-Time Systems

22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS)

D. Trilla, C. Hernández, J. Abella, and F. Cazorla
Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns

ISORC 2016 19th IEEE Symposium On Real-Time Computing

S. Milutinovic, J. Abella, and F. Cazorla
Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis

16th International Workshop on Worst-Case Execution Time Analysis (WCET)

E. Díaz, J. Abella, E. Mezzetti, I. Agirre, M. Azkarate-askasua, T. Vardanega, and F. Cazorla
Contention-Aware Performance Monitoring Counter Support for Real-Time MPSoCs

11th IEEE International Symposium on Industrial Embedded Systems (SIES)

J. Jalle, M. Fernández, J. Abella, J. Andersson, M. Patte, L. Fossati, M. Zulianello, and F. Cazorla
Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems

11th IEEE International Symposium on Industrial Embedded Systems (SIES)

J. Jalle, E. Quinones, J. Abella, L. Fossati, M. Zulianello, and F. Cazorla
Validating a Timing Simulator for the NGMP Multicore Processor

21st Data Systems In Aerospace Conference (DASIA)

J. Jalle, J. Abella, L. Fossati, M. Zulianello, and F. Cazorla
Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes

ICS '16 Proceedings of the 2016 International Conference on Supercomputing

D. Chasapis, M. Casas, M. Moreto, M. Schulz, E. Ayguade, J. Labarta, and M. Valero
TaskPoint: Sampled simulation of task-based programs

Performance Analysis of Systems and Software (ISPASS), 2016 IEEE International Symposium on

T. Grass, A. Rico, M. Casas, M. Moreto, and E. Ayguade
Supertask: Maximizing runnable-level parallelism in AUTOSAR applications

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) , Dresden, Germany, March 14-18, 2016

S. Kehr, M. Panic, E. Quinones, B. Boddeker, J. Becerril Sandoval, J. Abella, F. Cazorla, and G. Schäfer
Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems

IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Vienna, Austria, April 11-14, 2016

D. Trilla, J. Jalle, M. Fernández, J. Abella, and F. Cazorla
Sensible Energy Accounting with Abstract Metering for Multicore Systems

ACM Transactions on Architecture and Code Optimization (TACO)

Q. Liu, M. Moreto, J. Abella, F. Cazorla, D. A. Jiménez, and M. Valero
Bounding Resource-Contention Interference in the Next-Generation Multipurpose Processor (NGMP)

8th European Congress on Embedded Real Time Software and Systems (ERTS^2)

J. Jalle, M. Fernández, J. Abella, J. Andersson, M. Patte, L. Fossati, M. Zulianello, and F. Cazorla
A Detailed Methodology to Compute Soft Error Rates in Advanced Technologies

In Proceedings of the Design Automation and Test in Europe (DATE) Dresden, Germany

M. Riera, R. Canal, J. Abella, and A. González
A Lightweight OpenMP4 Run-time for Embedded Systems

21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, China

R. Vargas, S. Royuela, M. A. Serrano, X. Martorell, and E. Quinones
Response-Time Analysis of DAG Tasks under Fixed Priority Scheduling with Limited Preemption

In Proceedings of the Design Automation and Test in Europe (DATE) Dresden, Germany

M. A. Serrano, A. Melani, M. Bertogna, and E. Quinones

2015

P-SOCRATES: a Parallel Software Framework for Time-Critical Many-Core Systems

Microprocessors and Microsystems

L. MiguelPinho, V. Nelis, P. Meumeu Yomsi1, E. Quinones, M. Bertogna, P. Burgio, A. Marongiu, C. Scordino, P. Gai, M. Ramponi, and M. Mardiak
Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD)

C. Hernández, and J. Abella
Timing Characterization of OpenMP4 Tasking Model

Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2015 International Conference on

M. A. Serrano, A. Melani, R. Vargas, A. Marongiu, M. Bertogna, and E. Quinones

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