Adria Armejach Sanosa

2017

• Implications of non-volatile memory as primary storage for database management systems

  2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)

  N. UlMustafa, A. Armejach, O. Ozturk, A. Cristal, and O. S. Unsal

2016

• Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory

  Computing in Science & Engineering

  O. Arcas-Abella, A. Armejach, T. Hayes, G. Alp Malazgirt, O. Palomar, B. Salami, and N. Sonmez
• MUSA: A Multi-level Simulation Approach for Next-generation HPC Machines

  Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis

  T. Grass, C. Allande, A. Armejach, A. Rico, E. Ayguade, J. Labarta, M. Valero, M. Casas, and M. Moreto

2015

• Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches

  Computer Architecture and High Performance Computing (SBAC-PAD), 2015 27th International Symposium on

  A. Armejach, A. Cristal, and O. Unsal

2014

• Techniques to Improve Concurrency in Hardware Transactional Memory

  A. Armejach
• An empirical evaluation of High-Level Synthesis languages and tools for database acceleration

  24th International Conference on Field Programmable Logic and Applications (FPL), 2014

  O. Arcas, G. Ndu, N. Sönmez, M. Ghasempour, A. Armejach, J. Navaridas, W. Song, J. Mawer, A. Cristal, and M. Lujan

2013

• HARP: Adaptive Abort Recurrence Prediction for Hardware Transactional Memory

  IEEE Conference on High Performance Computing (HiPC 2013)

  A. Armejach, A. Negi, A. Cristal, O. Unsal, P. Stenström, and T. Harris
• Techniques to Improve Performance in Requester-wins Hardware Transactional Memory

  ACM Transactions on Architecture and Code Optimization

  A. Armejach, R T. J. Gil, A. Negi, O. Unsal, and A. Cristal

2012

• Transactional prefetching: narrowing the window of contention in hardware transactional memory

  Parallel Architectures and Compilation Techniques (PACT)

  A. Negi, A. Armejach, A. Cristal, O. Unsal, and P. Stenström

2011

• Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory

  Parallel Architectures and Compilation Techniques (PACT)

  A. Armejach, A. Seyedi, R T. J. Gil, I. Hur, O. Unsal, A. Cristal, and M. Valero