Publications

Primary tabs

Publications

V. Gajinov, Eric, I., Stojanovic, S., Milutinovic, V., Unsal, O., Ayguade, E., and Cristal, A., “A Case Study of Hybrid Dataflow and Shared-memory Programming Models: Dependency-based Parallel Game Engine”, 26th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2014. Pierre Sens, Philippe O. A. Navaux, Paris, France, pp. 1–8, 2014.
M. Casas and Bronevetsky, G., “Active Measurement of Memory Resource Consumption”, 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS) . 2014.
M. Casas and Bronevetsky, G., “Active Measurement of the Impact of Network Switch Utilization on Application Performance”, 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS). 2014.
T. Hussain, Palomar, O., Unsal, O., Cristal, A., Ayguade, E., and Valero, M., “Advanced Pattern based Memory Controller for FPGA based HPC Applications”, International Conference on High Performance Computing {&} Simulation, HPCS 2014. IEEE, Bologna, Italy, pp. 287–294, 2014.
T. Hussain, Palomar, O., Cristal, A., Unsal, O., Ayguade, E., and Valero, M., “AMMC: Advanced Multi-core Memory Controller”, 13th International Conference on Field Programmable Technology (FPT 2014). Shangai, China, 2014.
P. Fuentes, Bosque, J. L., Beivide, R., Valero, M., and Minkenberg, C., “Characterizing the Communication Demands of the Graph500 Benchmark on a Commodity Cluster”, International Symposium on Big Data Computing (BDC 2014). IEEE/ACM, London, UK, 2014.
L. Vilanova, Ben-Yehuda, M., Navarro, N., Etsion, Y., and Valero, M., “CODOMs: Protecting Software with Code-centric Memory Domains”, 41st International Symposium on Computer Architecture (ISCA). Minneapolis, MN, United States, 2014.
Q. Liu, Moreto, M., Abella, J., Cazorla, F., and Valero, M., “DReAM: Per-Task DRAM Energy Metering in Multicore Systems”, 20th International EUROPAR Conference. European Conference on Parallel and Distributed Computing. Springer, Porto, Portugal, pp. 111–123, 2014.
M. Duric, Palomar, O., Smith, A., Milan Stanic, Unsal, O., Cristal, A., and Valero, M., “Dynamic-Vector Execution on a General Purpose EDGE Chip Multiprocessor”, 14th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2014). Samos, Greece, pp. 18–25, 2014.
I. Tanasic, Gelado, I., Cabezas, J., Ramirez, A., Navarro, N., and Valero, M., “Enabling Preemptive Multiprogramming on GPUs”, 41st International Symposium on Computer Architecture (ISCA). Minneapolis, MN, United States, 2014.
Milan Stanic, Palomar, O., Ivan Ratkovic, Duric, M., Unsal, O., Cristal, A., and Valero, M., “Evaluation of vectorization potential of Graph500 on Intels Xeon Phi”, International Conference on High Performance Computing {&} Simulation, HPCS 2014. IEEE, Bologna, Italy, pp. 47–54, 2014.
T. Hussain, Sönmez, N., Palomar, O., Unsal, O., Cristal, A., Ayguade, E., and Valero, M., “PAMS: Pattern Aware Memory System for Embedded Systems”, ReConFig - International Conference on ReConFifurable Computing and FPGAs. Cancun, Mexico, 2014.
T. Hussain, Palomar, O., Unsal, O., Cristal, A., Ayguade, E., and Valero, M., “PVMC: Programmable Vector Memory Controller”, IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2014). IEEE, Zurich, Switzerland, pp. 240–247, 2014.
Milan Stanic, Palomar, O., Ivan Ratkovic, Duric, M., Unsal, O., and Cristal, A., “VALib and SimpleVector: tools for rapid initial research on vector architectures”, ACM International Conference on Computing Frontiers. ACM, Cagliari, Italy, 2014.
M. Valero, Moreto, M., Casas, M., Ayguade, E., and Labarta, J., “Runtime-Aware Architectures: A First Approach”, International Journal on Supercomputing Frontiers and Innovations, vol. 1. pp. 29-44, 2014.
H. Cook, Moreto, M., Bird, S., Dao, K., Patterson, D. A., and Asanović, K., “A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness”, Proceedings of the 40th Annual International Symposium on Computer Architecture. ACM, New York, NY, USA, pp. 308–319, 2013.
M. Garcia, Vallejo, E., Beivide, R., Valero, M., and Rodriguez, G., “OFAR-CM: Efficient Dragonfly Networks with Simple Congestion Management”, 2013 IEEE 21st Annual Symposium on High-Performance Interconnects (HOTI)2013 IEEE 21st Annual Symposium on High-Performance Interconnects. IEEE, San Jose, CA, USA, pp. 55-62, 2013.
M. Schulz, Bhatele, A., Belak, J., Bremer, P. - T., Casas, M., Bronevetsky, G., Gamblin, T., Isaacs, K., Laguna, I., Levine, J., Pascucci, V., Richards, D., and Rountree, B., “Performance Analysis Techniques for the Exascale Co-Design Process”, Proceedings of International Conference on Parallel Computing (PARCO). 2013.
C. Camarero, Vallejo, E., Martinez, C., Moreto, M., and Beivide, R., “Task Mapping in Rectangular Twisted Tori”, Proceedings of the High Performance Computing Symposium. Society for Computer Simulation International, San Diego, CA, USA, pp. 15:1–15:11, 2013.
J. A. Colmenares, Eads, G., Hofmeyr, S., Bird, S., Moreto, M., Chou, D., Gluzman, B., Roman, E., Bartolini, D. B., Mor, N., Asanović, K., and Kubiatowicz, J. D., “Tessellation: refactoring the OS around explicit resource containers with continuous adaptation”, Proceedings of the 50th Annual Design Automation Conference. ACM, New York, NY, USA, pp. 76:1–76:10, 2013.

Pages