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2024

Practically Tackling Memory Bottlenecks of Graph-Processing Workloads

38th IEEE International Parallel & Distributed Processing Symposium (IPDPS)

A. ValentinJamet, G. Vavouliotis, D. A. Jiménez, L. Álvarez, and M. Casas
A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering

2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)

A. ValentinJamet, G. Vavouliotis, D. A. Jiménez, L. Álvarez, and M. Casas

2022

Page Size Aware Cache Prefetching

55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

G. Vavouliotis, G. Chacon, L. Álvarez, P. V. Gratz, D. A. Jiménez, and M. Casas

2021

Exploiting Page Table Locality for Agile TLB Prefetching

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)

G. Vavouliotis, L. Álvarez, V. Karakostas, K. Nikas, N. Koziris, D. A. Jiménez, and M. Casas

2020

Characterizing the impact of last-level cache replacement policies on big-data workloads

Proceedings of the 2020 IEEE International Symposium on Workload Characterization (IISWC)

A. ValentinJamet, L. Alavarez, D. A. Jiménez, and M. Casas

2016

Sensible Energy Accounting with Abstract Metering for Multicore Systems

ACM Transactions on Architecture and Code Optimization (TACO)

Q. Liu, M. Moreto, J. Abella, F. Cazorla, D. A. Jiménez, and M. Valero

2010

2009

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