Publications

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International Conferences
V. Subotic, Sancho, J. C., Labarta, J., and Valero, M., A simulation framework to automatically analyze the communication-computation overlap in scientific applications. IEEE International Conference on Cluster Computing, 2011.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Torrellas, J., and Valero, M., Software Trace Cache, International Conference on Supercomputing (ICS'1999). pp. 119-126, 1999.
C. Boneti, Cazorla, F., Gioiosa, R., Cher, C. - Y., Buyuktosunoglu, A., and Valero, M., Software-Controlled Priority Characterization of POWER5 Processor. Beijing, China, 2008.
J. J. Alastruey, Monreal, T., Viñals, V., and Valero, M., Speculative Early Register Release. ACM International Conference on Computing Frontiers, 2006.
G. Kestor, Gioiosa, R., Harris, T., Cristal, A., Unsal, O., Valero, M., and Hur, I., STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems, The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT). 2011.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., Stream Predictor Guided Instruction Decoding, XV Jornadas de Paralelismo. pp. 184-189, 2004.
A. Falcón, Santana, O. J., Medina, P., Fernández, E., Ramirez, A., and Valero, M., Studying New Ways for Improving Adaptive History Length Branch Predictors, 4th International Symposium on High Performance Computing (ISHPC-4). Kansai Science City (Japan), pp. 271-279, 2002.
N. Rajovic, Carpenter, P., Gelado, I., Puzovic, N., Ramirez, A., and Valero, M., Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?, SC13: International Conference for High Performance Computing, Networking, Storage and Analysis. Denver, United States, pp. 40–40, 2013.
G. Yalcin, Unsal, O., Cristal, A., Hur, I., and Valero, M., SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, pp. 199–200, 2011.
S. Stipić, Tomić, S., Zyulkyarov, F., Cristal, A., Ünsal, O. S., and Valero, M., TagTM - accelerating STMs with hardware tags for fast meta-data access, DATE. pp. 39-44, 2012.
N. Sonmez, Harris, T., Cristal, A., Unsal, O., and Valero, M., Taking the heat off transactions: Dynamic selection of pessimistic concurrency control, Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing. IEEE Computer Society, Washington, DC, USA, pp. 1–10, 2009.
Y. Etsion, Cabarcas, F., Rico, A., Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: An Out-of-Order Task Pipeline, IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43). pp. 89-100, 2010.
M. Solinas, Badia, R. M., Bodin, F., Cohen, A., Evripidou, P., Faraboschi, P., Navarro, N., and Valero, M., The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices, Euromicro Conference on Digital System Design, DSD 2013. IEEE Computer Society, Santander, Spain, pp. 272–279, 2013.
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., Thread to Core Assignment in SMT On-Chip Multiprocessors, 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09). 2009.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems. In 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, Bangalore, India, 2010.
E. Fernández, Cazorla, F., Ramirez, A., Knijnenburg, P., Sakellariou, R., and Valero, M., Throughput versus Quality of Service in SMT processors, Euromicro-DSD (Digital System Design). Euromicro-DSD (Digital System Design), 2004.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
N. Sönmez, Arcas, O., Pflucker, O., Cristal, A., Unsal, O., Hur, I., Singh, S., and Valero, M., TMbox: A Flexible and Reconfigurable 16-core Hybrid Transactional Memory System, The 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011). Salt Lake City, United States, pp. 1–8, 2011.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., {TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
V. Smiljkovic, Nowack, M., Miletic, N., Harris, T., Unsal, O., Cristal, A., and Valero, M., TM-dietlibc: A TM-aware Real-world System Library, The 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013). IEEE, Boston, United States, 2013.
A. Falcón, Santana, O. J., Ramirez, A., and Valero, M., Tolerating branch predictor latency on SMT, 5th International Symposium on High Performance Computing (ISHPC-V). Tokio (Japan), pp. 86-98, 2003.
A. Ramirez, Larriba-Pey, J. L., Navarro, C., Serrano, X., Torrellas, J., and Valero, M., Trace Cache Redundancy, X Jornadas de Paralelismo. pp. 39-44, 1999.
A. Ramirez, Larriba-Pey, J. L., and Valero, M., Trace Cache Redundancy: Red & Blue Traces, Sixth International Symposium on High-Performance Computer Architecture (HPCA'2000). pp. 325-333, 2000.
A. Rico, Ramirez, A., and Valero, M., Trace Filtering of Multithreaded Applications for CMP Memory Simulation, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013). Austin, United States, pp. 134–135, 2013.
A. Rico, Duran, A., Cabarcas, F., Etsion, Y., Ramirez, A., and Valero, M., Trace-driven simulation of multithreaded applications, 2011 IEEE International Symposium on Performance Analysis of Systems and Software. p. 87--96, 2011.
V. J. Jiménez, Gioiosa, R., Kursun, E., Cazorla, F., Cher, C. - Y., Buyuktosunoglu, A., Bose, P., and Valero, M., Trends and techniques for energy efficient architectures. The 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), 2010.
M. Pericas, González, R., Cazorla, F., Cristal, A., Veidenbaum, A., Jiménez, D. A., and Valero, M., A two-level Load/Store Queue based on Execution Locality. In International Symposium on Computer Architecture. Beijing, China, 2008.
A. Armejach, Seyedi, A., Gil, R. T. J., Hur, I., Unsal, O., Cristal, A., and Valero, M., Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, pp. 360–370, 2011.
T. Hayes, Palomar, O., Unsal, O., Cristal, A., and Valero, M., Vector Extensions for Decision Support DBMS Acceleration, The 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO45). pp. 166-176, 2012.
M. Pericas, Chaves, R., Gaydadjiev, G. N., Valero, M., and Vassiliadis, S., Vectorized AES Core for high-throughput secure environments. VECPAR'08, 2008.
E. Salami and Valero, M., A Vector-uSIMD-VLIW Architecture for Multimedia Applications. ICPP, IEEE International Conference on Parallel Processing, 2005.
Journal
M. Paolieri, Quiñones, E., Cazorla, F., and Valero, M., An Analyzable Memory Controller for Hard Real-Time CMPs, IEEE Embedded Systems Letters, vol. 1, no. 4. 2009.
B. Maric, Abella, J., and Valero, M., Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22. pp. 266-275, 2014.
M. Araya-Polo, Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J. M., Ayguadé, E., Navarro, N., and Valero, M., Assessing Accelerator-based HPC Reverse Time Migration, Transactions on Parallel and Distributed Systems, Special Issue on Accelerators, vol. 22(1). pp. 147-162, 2011.
A. Rico, Ramirez, A., and Valero, M., Available task-level parallelism on the Cell BE, Scientific Programming, vol. 17, no. 1-2. pp. 59-76, 2009.
A. Falcón, Stark, J., Ramirez, A., Lai, K., and Valero, M., Better branch prediction through prophet/critic hybrids, IEEE Micro, vol. 25, no. 1. pp. 80-89, 2005.
V. Jimenez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications., IEEE Micro. 2011.
V. Jimenez, Cazorla, F., Gioiosa, R., Valero, M., Boneti, C., Kursun, E., Cher, C., Isci, C., Buyuktosunoglu, A., and Bose, P., Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper), IEEE Journal of Emerging and Selected Topics in Circuits and Systems. 2011.
C. Luque, Moretó, M., Cazorla, F. J., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU Accounting for Multicore Processors, IEEE Transactions on Computers, vol. 61. pp. 251–264, 2012.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU accounting in CMP Processors. In IEEE Computer Architecture Letters. Volume 9, 2009.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., DIA: A Complexity-Effective Decoding Architecture, IEEE Transactions on Computers, vol. 58, no. 4. pp. 448-462, 2009.
J. Vidal, March, M., Cerdá, L., Corbal, J., and Valero, M., A DRAM/SRAM Memory Scheme for Fast Packet Buffers. IEEE Transactions on Computers, 2006.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Dynamic Cache Partitioning Based on the MLP on Cache Misses., Transactions on HiPEAC, vol. 3, no. 1. pp. 1-21, 2008.
D. Ortega, Valero, M., and Ayguadé, E., Dynamic Memory Instruction Bypassing. IJPP, International Journal on Parallel Processing . Plenun Published Corporation. Special issue on selected papers from ICS-2003, 2004.
E. Salami and Valero, M., Dynamic Memory Interval Test vs. Interprocedural Pointer Analiysis in Multimedia Applications. ACM Transactions on Architecture and Code Optimization, TACO Journal, 2005.
O. J. Santana, Ramirez, A., and Valero, M., Enlarging Instruction Streams, IEEE Transactions on Computers, vol. 56, no. 10. pp. 1342-1357, 2007.
M. Moreto, Cazorla, F., Ramirez, A., and Valero, M., Explaining Dynamic Cache Partitioning Speed Ups, IEEE Computer Architecture Letters, vol. 6, no. 1. pp. 1-12, 2007.
C. Luque, Moreto, M., Cazorla, F. J., and Valero, M., Fair CPU Time Accounting in CMP+SMT Processors, ACM Trans. Archit. Code Optim., vol. 9. ACM, New York, NY, USA, pp. 50:1–50:25, 2013.
F. Cazorla, Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A., and Valero, M., Feasibility of QoS for SMT by Resource Allocation., Lecture Notes in Computer Science (LNCS) , vol. 3149/2004. 2004.
M. Moreto, Cazorla, F., Ramirez, A., Sakellariou, R., and Valero, M., FlexDCP: a QoS framework for CMP architectures, ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, vol. 43, no. 2. pp. 86-96, 2010.

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