Publications

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International Conferences
Salami, E. & Valero, M. A Vector-uSIMD-VLIW Architecture for Multimedia Applications. (2005).
Journal
Paolieri, M., Quiñones, E., Cazorla, F. & Valero, M. An Analyzable Memory Controller for Hard Real-Time CMPs. IEEE Embedded Systems Letters 1, (2009).
Araya-Polo, M., Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J.M., Ayguadé, E., Navarro, N. & Valero, M. Assessing Accelerator-based HPC Reverse Time Migration. Transactions on Parallel and Distributed Systems, Special Issue on Accelerators 22(1), 147-162 (2011).
Rico, A., Ramirez, A. & Valero, M. Available task-level parallelism on the Cell BE. Scientific Programming 17, 59-76 (2009).
Falcón, A., Stark, J., Ramirez, A., Lai, K. & Valero, M. Better branch prediction through prophet/critic hybrids. IEEE Micro 25, 80-89 (2005).
Jimenez, V., Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P. & Valero, M. A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications. IEEE Micro (2011).
Jimenez, V., Cazorla, F., Gioiosa, R., Valero, M., Boneti, C., Kursun, E., Cher, C., Isci, C., Buyuktosunoglu, A. & Bose, P. Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper). IEEE Journal of Emerging and Selected Topics in Circuits and Systems (2011).
Luque, C., Moretó, M., Cazorla, F.J., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. CPU Accounting for Multicore Processors. IEEE Transactions on Computers 61, 251–264 (2012).
Luque, C., Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A. & Valero, M. CPU accounting in CMP Processors. (2009).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. DIA: A Complexity-Effective Decoding Architecture. IEEE Transactions on Computers 58, 448-462 (2009).
Vidal, J., March, M., Cerdá, L., Corbal, J. & Valero, M. A DRAM/SRAM Memory Scheme for Fast Packet Buffers. (2006).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Dynamic Cache Partitioning Based on the MLP on Cache Misses. Transactions on HiPEAC 3, 1-21 (2008).
Ortega, D., Valero, M. & Ayguadé, E. Dynamic Memory Instruction Bypassing. (2004).
Salami, E. & Valero, M. Dynamic Memory Interval Test vs. Interprocedural Pointer Analiysis in Multimedia Applications. (2005).
Santana, O.J., Ramirez, A. & Valero, M. Enlarging Instruction Streams. IEEE Transactions on Computers 56, 1342-1357 (2007).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Explaining Dynamic Cache Partitioning Speed Ups. IEEE Computer Architecture Letters 6, 1-12 (2007).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernandez, E., Ramirez, A. & Valero, M. Feasibility of QoS for SMT by Resource Allocation. Lecture Notes in Computer Science (LNCS) 3149/2004, (2004).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 0163-5980 (2009).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 86-96 (2010).
Álvarez, C., Corbal, J. & Valero, M. Fuzzy Memoization for Floating Point Multimedia Applications. (2005).
Monreal, T., Viñals, V., González, A. & Valero, M. Hardware Support for Early Register Release. (2005).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. High Performance and Low Power VLIW for Numerical Applications. (2004).
Azevedo, A., Meenderinck, C., Juurlink, B., Tereckho, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A. & Valero, M. A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers 4, (2009).
Salami, E. & Valero, M. Initial Evaluation of Multimedia Extensions on VLIW Architectures. (2004).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Instruction Fetch Architectures and Code Layout Optimizations. Proceedings of the IEEE 89, 1588-1609 (2001).
Cristal, A., Santana, O.J., Cazorla, F., Galluzzi, M., Ramírez, T., Pericàs, M. & Valero, M. Kilo-instruction Processors: Overcoming the Memory Wall. IEEE Micro 25, 48–57 (2005).
Monreal, T., Viñals, V., González, J., González, A. & Valero, M. Late Allocation and Early Release of Physical Registers. (2004).
Falcón, A., Santana, O.J., Ramirez, A. & Valero, M. A latency conscious SMT branch predictor architecture. International Journal of High Performance Computing and Networking (IJHPCN) 2, 11-21 (2004).
Valero, M., Santana, O.J., Ramirez, A. & Larriba-Pey, J.L. A Low Complexity Fetch Architecture for High Performance Superscalar Processors. ACM Transactions on Architecture and Compiler Optimizations (TACO) 1, 220-245 (2004).
Santana, O.J., Ramirez, A., Larriba-Pey, J.L. & Valero, M. A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors. ACM Transactions on Architecture and Code Optimization 1, 220-245 (2004).
Nesbit, K.J., Moreto, M., Cazorla, F., Ramirez, A., Valero, M. & Smith, J.E. Multicore Resource Management. IEEE Micro 28, 6-16 (2008).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN) 2, (2004).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. Performance and Power Evaluation of Clustered VLIW Processors with Functional Units. (2004).
Álvarez, M., Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C. & Juurlink, B. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. Avances en Sistemas e Informática 6, 219-228 (2009).
Morad, T., Weiser, U., Kolodny, A., Valero, M. & Ayguadé, E. Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors. (2006).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. Power and Performace Evaluation of Widened and Clustered VLIW Cores. (2005).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. Predictable Performance in SMT processors: Synergy Between the OS and SMTs. IEEE Transactions on Computers 55, 785-799 (2006).
Cazorla, F., Pajuelo, A., Santana, O.J., Fernandez, E. & Valero, M. On the Problem of Evaluating the Performance of Multiprogrammed Workloads. . IEEE Transactions on Computers 59, (2010).
Cazorla, F., Ramirez, A., Valero, M., Knijnenburg, P., Sakellariou, R. & Fernández, E. QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24, 24-31 (2004).
Zalamea, J., Llosa, J., Ayguadé, E. & Valero, M. Register-constrained Modulo Scheduling. (2004).
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Scalable multicore architectures for long DNA sequence comparison. Concurrency and Computation Practice and Experience 23, (2011).
Boneti, C., Cazorla, F., Gioiosa, R. & Valero, M. Scheduling Real-Time Systems With Explicit Resource Allocation Processors. (2008).
González, J., Giménez, J., Casas, M., Moretó, M., Ramirez, A., Labarta, J. & Valero, M. Simulating Whole Supercomputer Applications. IEEE Micro 31, 32-45 (2011).
Rico, A., Cabarcas, F., Villavieja, C., Pavlovic, M., Vega, A., Etsion, Y., Ramirez, A. & Valero, M. On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels. ACM Transactions on Architecture and Code Optimization 8, 36 (2012).
Morari, A., Boneti, C., Cazorla, F.J., Gioiosa, R., Cher, C.-Y., Buyuktosunoglu, A., Bose, P. & Valero, M. SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Transactions on Computers 00, (2012).
Zalamea, J., Llosa, J., Ayguadé, E. & Valero, M. Software and Hardware Techniques to Optimize Register File Utilization in VLIW. (2004).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. Software Trace Cache. IEEE Transactions on Computers 54, 22-35 (2005).
Ramirez, A., Larriba-Pey, J.L., Navarro, C., Valero, M. & Torrellas, J. Software Trace Cache for Commercial Applications. International Journal of Parallel Programming 30, 373-395 (2002).
Pajuelo, A., González, A. & Valero, M. Speculative Execution for Hiding Memory Latency. (2005).
Ramirez, A., Larriba-Pey, J.L. & Valero, M. A Stream Processor Front-end. IEEE Technical Committee on Computer Architecture Newsletter 10-13 (2000).

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