Publications

Export 31 results:
Sort by: Author Title [ Type (Asc)] Year
Filters: Author is Enrique Fernández  [Clear All Filters]
Conference Paper
García, A., Santana, O.J., Fernández, E., Medina, P., Cristal, A. & Valero, M. Reducing the Activity of Instruction Renaming in Loop Structures. II Congreso Español de Informática (CEDI 2007) (2007).
García, A., Medina, P., Fernández, E., Santana, O.J., Cristal, A. & Valero, M. Towards the Loop Processor Architecture. XVI Jornadas de Paralelismo (2005).
International Conferences
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. Architectural Support for Real-Time Task Scheduling in SMT Processors. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES-2005) (2005).
Santana, O.J., Falcón, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. A Comprehensive Analysis of Indirect Branch Prediction. 4th International Symposium on High Performance Computing (ISHPC-4) 133-141 (2002).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. DCache Warn: An I-Fetch Policy To Increase SMT Efficiency. 18th International Parallel and Distributed Processing Symposium (IPDPS-2004) (2004).
Cazorla, F., Ramirez, A., Valero, M. & Fernández, E. Dynamically Controlled Resource Allocation in SMT Processors. 37th Annual International Symposium on Microarchitecture (MICRO-37) 171-182 (2004).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. FAME: FAirly MEasuring Multithreaded Architectures. (2007).at <http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4336221>
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. Implicit vs. Explicit Resource Allocation in SMT Processors. 2004 Euromicro Symposium on Digital Systems Design (DSD 2004) 44-51 (2004).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Improving Memory Latency Aware Fetch Policies for SMT Processors. 5th International Symposium on High Performance Computing (ISHPC-V) 70-85 (2003).at <http://personals.ac.upc.edu/fcazorla/articles/fcazorla_ishpc2003.pdf>
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. Predictable Performance in SMT Processors. Computing Frontiers (CF'04) (2004).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. On the Problem of Minimizing Workload Execution Time in SMT Processors. International Conference on Embedded Computer Systems: Architectures, Modelling, and Simulation (SAMOS VII) 66-73 (2007).at <http://dx.doi.org/10.1109/ICSAMOS.2007.4285735>
Cazorla, F., Knijnenburg, P., Sakellarious, R., Fernández, E., Ramirez, A. & Valero, M. Quality of service for Simultaneous Multithreading Processors. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems 67-70 (2005).
Falcón, A., Santana, O.J., Medina, P., Fernández, E., Ramirez, A. & Valero, M. Studying New Ways for Improving Adaptive History Length Branch Predictors. 4th International Symposium on High Performance Computing (ISHPC-4) 271-279 (2002).
Fernández, E., Cazorla, F., Ramirez, A., Knijnenburg, P., Sakellariou, R. & Valero, M. Throughput versus Quality of Service in SMT processors. Euromicro-DSD (Digital System Design) (2004).
Journal
Fernández, E., Torrents, D., Chillarón, J., Del Rio, M., Zorzano, A. & Palacín, M. Basolateral LAT-2 has a major role in the transepithelial flux of L-cystine in the renal proximal tubule cell line OK. (2003).
Torrents, D., Estevez, R., Pineda, M., Fernández, E., Lloberas, J., Shi, Y.B., Zorzano, A. & Palacín, M. Identification and characterization of a membrane protein (y+L amino acid transporter-1) that associates with 4F2hc to encode the amino acid transport activity y+L. A candidate gene for lysinuric protein intolerance. (1998).
Fernández, E., Torrents, D., Zorzano, A., Palacín, M. & Chillarón, J. Identification and functional characterization of a novel low affinity aromatic-preferring amino acid transporter (arpAT). One of the few proteins silenced during primate evolution. (2005).
Pineda, M., Fernández, E., Torrents, D., Estevez, R., López, C., Camps, M., Lloberas, J., Zorzano, A. & Palacín, M. Identification of a membrane protein, LAT-2, that Co-expresses with 4F2 heavy chain, an L-type amino acid transport activity with broad specificity for small and large zwitterionic amino acids. (1999).
Feliubadalo, L., Font, M., Purroy, J., Rousaud, F., Estivill, X., Nunes, V., Reig, N., Fernández, E., Estevez, R., Pineda, M., Torrents, D., Camps, M., Lloberas, J., Zorzano, A. & Palacín, M. Non-type I cystinuria caused by mutations in SLC7A9, encoding a subunit (bo,+AT) of rBAT. (1999).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Optimizing Long-Latency-Load-Aware Fetch Policies for SMT Processors. International Journal of High Performance Computing and Networking (IJHPCN) 2, (2004).
Cazorla, F., Knijnenburg, P., Sakellariou, R., Fernández, E., Ramirez, A. & Valero, M. Predictable Performance in SMT processors: Synergy Between the OS and SMTs. IEEE Transactions on Computers 55, 785-799 (2006).
Cazorla, F., Ramirez, A., Valero, M., Knijnenburg, P., Sakellariou, R. & Fernández, E. QoS for High-Performance SMT Processors in Embedded Systems. IEEE Micro 24, 24-31 (2004).
National Conferences
García, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. Analisis y caracterización de los bucles. XIII Jornadas de Paralelismo (2002).
Falcón, A., Santana, O.J., Medina, P., Fernández, E., Ramirez, A. & Valero, M. An Analysis of Dynamic History Length Fitting. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Dynamically Controlled Resource Allocation in SMT. XVI Jornadas de Paralelismo. Granada (2005).
Cazorla, F., Medina, P., Fernández, E., Ramirez, A. & Valero, M. Estudio y evaluación de mecanismos de control de la Especulación. In XIII Jornadas de Paralelismo, Lleida (Spain) (2002).
Santana, O.J., Falcón, A., Fernández, E., Medina, P., Ramirez, A. & Valero, M. An In-Depth Evaluation of the Multi-Stage Cascaded Predictor. XII Jornadas de Paralelismo, Valencia (Spain) (2001).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. Looking for novel ways to obtain fair measurements in multithreaded architectures. (2006).
Workshops
Cazorla, F., Fernández, E., Ramirez, A. & Valero, M. Approaching a Smart Sharing of Resources in SMT Processors. Workshop on Complexity-Effective Design (WCED) (2004).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. Measuring the Performance of Multithreaded Processors. (2007).
Vera, J., Cazorla, F., Pajuelo, A., Santana, O.J., Fernández, E. & Valero, M. A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures. (2006).