Publications

Export 89 results:
Author Title Type [ Year(Desc)]
Filters: Author is Francisco Cazorla  [Clear All Filters]
2009
V. Cakarevic, Radojkovic, P., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Characterizing the resource-sharing levels in the UltraSPARC T2 Processor. In 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), New York, USA, 2009.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU accounting in CMP Processors. In IEEE Computer Architecture Letters. Volume 9, 2009.
M. Paolieri, Quiñones, E., Cazorla, F., and Valero, M., Efficient Execution of Mixed Application Workloads in a Hard Real-Time. In Workshop on Reconciling Performance with Predictability (RePP) Oct. 15, 2009, during the ESWEEK, Grenoble, France, 2009.
M. Moreto, Cazorla, F., Ramirez, A., Sakellariou, R., and Valero, M., FlexDCP: a QoS framework for CMP architectures, ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, vol. 43, no. 2. pp. 0163-5980, 2009.
M. Paolieri, Quiñones, E., Cazorla, F., Bernat, G., and Valero, M., Hardware Support for WCET Analysis of Multicore Systems. In International Symposium on Computer Architecture, Austin, USA, 2009.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. In International Symposium on Parallel Architectures and Compilation Techniques, North Carolina, USA, 2009.
K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., pseudo-LRU based Cache Partitioning Algorithms. In International Symposium on Parallel Architectures and Compilation Techniques, North Carolina, USA, 2009.
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., Thread to Core Assignment in SMT On-Chip Multiprocessors, 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09). 2009.
E. Quiñones, Berger, E. D., Bernat, G., and Cazorla, F., Using Randomized Caches in Probabilistic Real-Time Systems. In 21st Euromicro Conference on Real-Time Systems (ECRTS 09), Dublin, Ireland, 2009.
2010
K. Kedzierski, Moreto, M., Cazorla, F., and Valero, M., Adapting Cache Partitioning Algorithms to Real pseudo-LRU Replacement Policies. In 24th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Atlanta, Georgia, 2010.
V. J. Jiménez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., and Valero, M., A Case for Energy Aware Accounting in Large Scale Computing Facilities: Cost Metrics and Implications for Processor Design.. Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA, 2010.
M. Moreto, Cazorla, F., Ramirez, A., Sakellariou, R., and Valero, M., FlexDCP: a QoS framework for CMP architectures, ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, vol. 43, no. 2. pp. 86-96, 2010.
M. Moreto, Paolieri, M., Abella, J., Quiñones, E., Cazorla, F., and Valero, M., Hard Real-Time Capable Multicore Processors for Space Applications. ESTEC 1st Networking/Partnering Day, 2010.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., and Valero, M., ITCA: Inter-Task Conflict-Aware CPU Accounting for CMPs. XXI Jornadas de Paralelismo, 2010.
M. Moreto, Cazorla, F., Sakellariou, R., and Valero, M., Load Balancing Using Dynamic Cache Allocation. ACM International Conference on Computing Frontiers (CF), 2010.
T. Ungerer, Cazorla, F., Sainrat, P., Bernat, G., Petrov, Z., Casse, H., Rochange, C., Quiñones, E., Uhrig, S., Gerdes, M., Guliashvili, I., Houston, M., Kluge, F., and Met, S., MERASA: Multi-Core Execution of Hard Real-Time Applications Supporting Analysability. IEEE Micro 2010, Special Issue on European Multicore Processing Projects, Vol. 30, No. 5, October 2010, 2010.
K. Kedzierski, Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., Power and Performance Aware Reconfigurable Cache for CMPs. Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, 2010.
V. J. Jiménez, Boneti, C., Cazorla, F., Gioiosa, R., Kursun, E., Cher, C. - Y., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., Power and Thermal Characterization of POWER6 System. The 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010.
F. Cazorla, Pajuelo, A., Santana, O. J., Fernandez, E., and Valero, M., On the Problem of Evaluating the Performance of Multiprogrammed Workloads. , IEEE Transactions on Computers, vol. 59, no. 12. IEEE, 2010.
P. Radojkovic, Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Thread to Strand Binding of Parallel Network Applications in Massive Multi-Threaded Systems. In 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, Bangalore, India, 2010.
V. J. Jiménez, Gioiosa, R., Kursun, E., Cazorla, F., Cher, C. - Y., Buyuktosunoglu, A., Bose, P., and Valero, M., Trends and techniques for energy efficient architectures. The 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), 2010.
L. Kosmidis, Quiñones, E., Abella, J., Cazorla, F., Bernat, G., and Berger, E. D., Use of randomized caches in hard real-time systems. 6th ACACES 2010 (Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems), 2010.
C. Boneti, Gioiosa, R., Cazorla, F., and Valero, M., Using hardware resource allocation to balance HPC applications, Parallel and Distributed Computing, Parallel and Distributed Computing, 2010.
2011
V. Jimenez, Cazorla, F., Gioiosa, R., Kursun, E., Isci, C., Buyuktosunoglu, A., Bose, P., and Valero, M., A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications., IEEE Micro. 2011.
V. Jimenez, Cazorla, F., Gioiosa, R., Valero, M., Boneti, C., Kursun, E., Cher, C., Isci, C., Buyuktosunoglu, A., and Bose, P., Characterizing Power and Temperature Behavior of POWER6-Based System. (invited paper), IEEE Journal of Emerging and Selected Topics in Circuits and Systems. 2011.
E. Quiñones, Abella, J., Cazorla, F., and Valero, M., Exploiting Intra-Task Slack Time of Load Operations for DVFS in Hard Real-Time Multi-core Systems, In Work in Progess (WiP), under the the 24nd Euromicro Conference on Real-Time Systems (ECRTS 2011). 2011.
B. Maric, Abella, J., Cazorla, F., and Valero, M., Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches, International Conference on Computing Frontiers (CF). pp. 12:1-12:2, 2011.
M. Paolieri, Quiñones, E., Cazorla, F., Davis, R. I., and Valero, M., IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems. 17th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2011), 2011.
Q. Liu, Moretó, M., Abella, J., and Cazorla, F., Online Performance Prediction in Processors with DVFS Capabilities, ACACES 2011. Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems. 2011.
A. Morari, Gioiosa, R., Wisniewski, R., Cazorla, F., and Valero, M., A Quantitative Analysis of OS Noise. Anchorage (Alaska) USA, 2011.
J. Abella, Quiñones, E., Cazorla, F., Sazeides, Y., and Valero, M., RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches. HiPEAC'11: 6th Int. Conference on High Performance and Embedded Architectures and Compilers, 2011.
J. Abella, Quiñones, E., Cazorla, F., Valero, M., and Sazeides, Y., RVC-based time-predictable faulty caches for safety-critical systems., IOLTS. IEEE, pp. 25-30, 2011.
M. Paolieri, Quiñones, E., Wolf, J., Petrov, Z., Cazorla, F., Uhrig, S., and Ungerer, T., A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-Threaded Hard Real-Time Tasks. 14th IEEE International Symposium on Object/Component/Service-oriented Real-time Distributed Computing (ISORC 2011), 2011.
J. Abella, Cazorla, F., Quiñones, E., Grasset, A., Yehia, S., Bonnot, P., Gizopoulos, D., Mariani, R., and Bernat, G., Towards improved survivability in safety-critical systems, International On-Line Testing Symposium (IOLTS). pp. 240-245, 2011.

Pages