Publications

Export 173 results:
Author Title Type [ Year(Desc)]
Filters: Author is Francisco Cazorla  [Clear All Filters]
2015
G. Fernandez, Abella, J., Quiñones, E., Fossati, L., Zulianello, M., Vardanega, T., and Cazorla, F., Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors, IEEE 18th International Symposium on Real-Time Distributed Computing, (ISORC). pp. 208-217, 2015.
S. Milutinovic, Abella, J., Hardy, D., Quiñones, E., Puaut, I., and Cazorla, F., Speeding up Static Probabilistic Timing Analysis, Architecture of Computing Systems – ARCS 2015, vol. 9017, no. Lecture Notes in Computer Science. pp. 236-247, 2015.
F. Wartel, Kosmidis, L., Gogonel, A., Baldovin, A., Stephenson, Z., Triquet, B., Quiñones, E., Lo, C., Mezzetti, E., Broster, I., Abella, J., Cucu-Grosjean, L., Vardanega, T., and Cazorla, F., Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms, DATE '15 Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition. pp. 397-402, 2015.
C. Hernandez, Abella, J., Cazorla, F., Andersson, J., and Gianarro, A., Towards Making a LEON3 Multicore Compatible with Probabilistic Timing Analysis, 20th Data Systems In Aerospace Conference (DASIA), Barcelona, Spain. 2015.
J. Abella, Hernandez, C., Quiñones, E., Cazorla, F., Conmy, P. Ryan, Azkarate-askasua, M., Perez, J., Mezzetti, E., and Vardanega, T., WCET Analysis Methods: Pitfalls and Challenges on their Trustworthiness, 10th IEEE International Symposium on Industrial Embedded Systems (SIES) . pp. 1-10, 2015.
2016
J. Jalle, Fernández, M., Abella, J., Andersson, J., Patte, M., Fossati, L., Zulianello, M., and Cazorla, F., Bounding Resource-Contention Interference in the Next-Generation Multipurpose Processor (NGMP), 8th European Congress on Embedded Real Time Software and Systems (ERTS^2). 2016.
P. Benedicte, Kosmidis, L., Quiñones, E., Abella, J., and Cazorla, F., A Confidence Assessment of WCET Estimates for Software Time Randomized Caches, 14th International Conference on Industrial Informatics (INDIN). IEEE, 2016.
J. Jalle, Fernández, M., Abella, J., Andersson, J., Patte, M., Fossati, L., Zulianello, M., and Cazorla, F., Contention-Aware Performance Monitoring Counter Support for Real-Time MPSoCs, 11th IEEE International Symposium on Industrial Embedded Systems (SIES). 2016.
J. Jalle, Quiñones, E., Abella, J., Fossati, L., Zulianello, M., and Cazorla, F., Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems, 11th IEEE International Symposium on Industrial Embedded Systems (SIES). 2016.
F. Cazorla, Abella, J., Andersson, J., Vardanega, T., Vatrinet, F., Bate, I., Broster, I., Azkarate-askasua, M., Wartel, F., Cucu-Grosjean, L., Cros, F., Farrall, G., Gogonel, A., Gianarro, A., Triquet, B., Hernandez, C., Lo, C., Maxim, C., Morales, D., Quiñones, E., Mezzetti, E., Kosmidis, L., Agirre, I., Fernández, M., Slijepcevic, M., Conmy, P. Ryan, and Talaboulma, W., Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis, 19th Euromicro Conference on Digital Systems Design (DSD). 2016.
L. Kosmidis, Compagnin, D., Morales, D., Mezzetti, E., Quiñones, E., Abella, J., Vardanega, T., and Cazorla, F., Measurement-Based Timing Analysis of the AURIX Caches, 16th International Workshop on Worst-Case Execution Time Analysis (WCET). 2016.
E. Díaz, Abella, J., Mezzetti, E., Agirre, I., Azkarate-askasua, M., Vardanega, T., and Cazorla, F., Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis, 16th International Workshop on Worst-Case Execution Time Analysis (WCET). 2016.
M. Panic, Hernandez, C., Quiñones, E., Abella, J., and Cazorla, F., Modeling High-Performance Wormhole NoCs for Critical Real-Time Embeddedd Systems, 22nd IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Viena, Austria. 2016.
S. Milutinovic, Abella, J., and Cazorla, F., Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns, ISORC 2016 19th IEEE Symposium On Real-Time Computing . 2016.
P. Benedicte, Kosmidis, L., Quiñones, E., Abella, J., and Cazorla, F., Modelling the Confidence of Timing Analysis for Time Randomised Caches, 11th IEEE International Symposium on Industrial Embedded Systems (SIES). IEEE, 2016.
T. Ungerer, Bradatsch, C., Frieb, M., Kluge, F., Mische, J., Stegmeier, A., Jahr, R., Gerdes, M., Zaykov, P., Matusova, L., Li, Z. Jian Jia, Petrov, Z., Böddeker, B., Kehr, S., Regler, H., Hugl, A., Rochange, C., Ozaktas, H., Cassé, H., Bonenfant, A., Sainrat, P., Lay, N., George, D., Broster, I., Quiñones, E., Panic, M., Abella, J., Hernandez, C., Cazorla, F., Uhrig, S., Rohde, M., and Pyka, A., Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore, ACM Trans. Embed. Comput. Syst., vol. 15. ACM, New York, NY, USA, pp. 53:1–53:27, 2016.
M. Slijepcevic, Fernández, M., Hernandez, C., Abella, J., Quiñones, E., and Cazorla, F., pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems, 19th Euromicro Conference on Digital Systems Design (DSD). 2016.
C. Hernandez, Abella, J., Gianarro, A., Andersson, J., and Cazorla, F., Random Modulo: a New Processor Cache Design for Real-Time Critical Systems, 53rd Design Automation Conference (DAC). 2016.
D. Trilla, Hernandez, C., Abella, J., and Cazorla, F., Resilient Random Modulo Cache Memories for Probabilistically-Analyzable Real-Time Systems, 22nd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS). IEEE, 2016.
Q. Liu, Moreto, M., Abella, J., Cazorla, F., Jiménez, D. A., and Valero, M., Sensible Energy Accounting with Abstract Metering for Multicore Systems, ACM Transactions on Architecture and Code Optimization (TACO), vol. 12, no. 11th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC). 2016.
L. Kosmidis, Vargas, R., Morales, D., Quiñones, E., Abella, J., and Cazorla, F., TASA: Toolchain-Agnostic Static Software Randomisation for Critical Real-Time Systems, 35th International Conference On Computer Aided Design (ICCAD). 2016.
P. Radojkovic, Carpenter, P., Moreto, M., Cakarevic, V., Verdú, J., Pajuelo, A., Cazorla, F., Nemirovsky, M., and Valero, M., Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach, IEEE Transactions on Computers, vol. 65, no. 1. pp. 256-269, 2016.
J. Jalle, Abella, J., Fossati, L., Zulianello, M., and Cazorla, F., Validating a Timing Simulator for the NGMP Multicore Processor, 21st Data Systems In Aerospace Conference (DASIA). 2016.

Pages