Export 18 results:Sort by: Author [ Title] Type Year
Filters: Author is Mateo Valero and First Letter Of Title is H [Clear All Filters]
Hybrid/Heterogeneous Programming with OmpSs and its Software/Hardware Implications. Programming Multi-Core and Many-Core Computing Systems (Wiley Series on Parallel and Distributed Computing) (2012).at <http://www.par.univie.ac.at/~pllana/manycore_book/>
Hybrid Transactional Memory to accelerate safe lock-based transactions. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003699.pdf>
Hybrid Parallel Programming with MPI/StarSs. Applications, Tools and Techniques on the Road to Exascale Computing (2012).
Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches. International Conference on Computing Frontiers (CF) 12:1-12:2 (2011).
A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers 4, (2009).
Hierarchical Gaussian Topologies. (2005).
Heterogeneity-Aware Architectures. XV Jornadas de Paralelismo 202-207 (2004).
HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications. 2007 IEEE International Symposium on Workload Characterization (IISWC-2007) 120-125 (2007).
hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture. XVI Jornadas de Paralelismo 59-66 (2005).
Hardware/Software Techniques for Assisted Execution Runtime Systems. The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE) (2012).
Hardware Transactional Memory with Operating System Support, HTMOS. Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par (2007).
Hardware Support for Accurate Per-task Energy Metering in Multicore Systems. ACM Trans. Archit. Code Optim. 10, 34:1–34:27 (2013).