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Ayguadé, E., Badia, R.M., Bellens, P., Bueno-Hedo, J., Duran, A., Etsion, Y., Farreras, M., Ferrer, R., Labarta, J., Marjanovic, V., Martinell, L., Martorell, X., Pérez, J.M., Planas, J., Ramirez, A., Teruel, X., Tsalouchidou, I. & Valero, M. Hybrid/Heterogeneous Programming with OmpSs and its Software/Hardware Implications. Programming Multi-Core and Many-Core Computing Systems (Wiley Series on Parallel and Distributed Computing) (2012).at <>
Vallejo, E., Harris, T., Cristal, A., Unsal, O. & Valero, M. Hybrid Transactional Memory to accelerate safe lock-based transactions. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008) (2008).at <>
Labarta, J., Marjanovic, V., Ayguadé, E., Badia, R.M. & Valero, M. Hybrid Parallel Programming with MPI/StarSs. Applications, Tools and Techniques on the Road to Exascale Computing (2012).
Maric, B., Abella, J., Cazorla, F. & Valero, M. Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches. International Conference on Computing Frontiers (CF) 12:1-12:2 (2011).
García, J., March, M., Cerdá, L., Corbal, J. & Valero, M. A Hybrid DRAM/SRAM Design for Fast Packet Buffers. (2004).
Azevedo, A., Meenderinck, C., Juurlink, B., Tereckho, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A. & Valero, M. A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers 4, (2009).
Pericas, M., Ayguadé, E., Zalamea, J., Llosa, J. & Valero, M. High Performance and Low Power VLIW for Numerical Applications. (2004).
Moreto, M., Martínez, C., Vallejo, E., Beivide, M. & Valero, M. Hierarchical Topologies for Large-Scale Two-Level Networks. (2005).
Moreto, M., Martínez, C., Beivide, R., Vallejo, E. & Valero, M. Hierarchical Gaussian Topologies. (2005).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. Heterogeneity-Aware Architectures. XV Jornadas de Paralelismo 202-207 (2004).
Álvarez, M., Salami, E., Ramirez, A. & Valero, M. HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications. 2007 IEEE International Symposium on Workload Characterization (IISWC-2007) 120-125 (2007).
Acosta, C., Falcón, A., Ramirez, A. & Valero, M. hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture. XVI Jornadas de Paralelismo 59-66 (2005).
Kestor, G., Gioiosa, R., Unsal, O., Cristal, A. & Valero, M. Hardware/Software Techniques for Assisted Execution Runtime Systems. The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE) (2012).
Tomić, S., Cristal, A., Unsal, O. & Valero, M. Hardware Transactional Memory with Operating System Support, HTMOS. Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par (2007).
Paolieri, M., Quiñones, E., Cazorla, F., Bernat, G. & Valero, M. Hardware Support for WCET Analysis of Multicore Systems. (2009).
Monreal, T., Viñals, V., González, A. & Valero, M. Hardware Support for Early Register Release. (2005).
Liu, Q., Moreto, M., Jimenez, V., Abella, J., Cazorla, F.J. & Valero, M. Hardware Support for Accurate Per-task Energy Metering in Multicore Systems. ACM Trans. Archit. Code Optim. 10, 34:1–34:27 (2013).
Moreto, M., Paolieri, M., Abella, J., Quiñones, E., Cazorla, F. & Valero, M. Hard Real-Time Capable Multicore Processors for Space Applications. (2010).