Publications

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E. Ayguadé, Badia, R. M., Bellens, P., Bueno-Hedo, J., Duran, A., Etsion, Y., Farreras, M., Ferrer, R., Labarta, J., Marjanovic, V., Martinell, L., Martorell, X., Pérez, J. M., Planas, J., Ramirez, A., Teruel, X., Tsalouchidou, I., and Valero, M., Hybrid/Heterogeneous Programming with OmpSs and its Software/Hardware Implications, in Programming Multi-Core and Many-Core Computing Systems (Wiley Series on Parallel and Distributed Computing) , Wiley Series on "Parallel and Distributed Computing"., John Wiley & Sons, Inc., 2012.
E. Vallejo, Harris, T., Cristal, A., Unsal, O., and Valero, M., Hybrid Transactional Memory to accelerate safe lock-based transactions, in 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008), Salt Lake City, UT, United States, 2008.
J. Labarta, Marjanovic, V., Ayguadé, E., Badia, R. M., and Valero, M., Hybrid Parallel Programming with MPI/StarSs, in Applications, Tools and Techniques on the Road to Exascale Computing, IOS Press, 2012.
B. Maric, Abella, J., Cazorla, F., and Valero, M., Hybrid High-Performance Low-Power and Ultra-Low Energy Reliable Caches, International Conference on Computing Frontiers (CF). pp. 12:1-12:2, 2011.
J. García, March, M., Cerdá, L., Corbal, J., and Valero, M., A Hybrid DRAM/SRAM Design for Fast Packet Buffers. HPRS. IEEE Workshop on High Performance Switching and Routing, 2004.
B. Maric, Abella, J., Cazorla, F. J., and Valero, M., Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation, ACM Transactions on Design Automation of Electronic Systems, vol. 20. 2014.
B. Maric, Abella, J., Cazorla, F. J., and Valero, M., Hybrid Cache Designs for Reliable Hybrid High and Ultra Low Voltage Operation, ACM Transactions on Design Automation of Electronic Systems, vol. 20. 2014.
A. Azevedo, Meenderinck, C., Juurlink, B., Tereckho, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A., and Valero, M., A Highly Scalable Parallel Implementation of H.264, Transactions on High-Performance Embedded Architectures and Compilers, vol. 4, no. 2. 2009.
M. Pericas, Ayguadé, E., Zalamea, J., Llosa, J., and Valero, M., High Performance and Low Power VLIW for Numerical Applications. IJHPCN. International Journal of High Performance Computing and Networking, 2004.
M. Moreto, Martínez, C., Vallejo, E., Beivide, M., and Valero, M., Hierarchical Topologies for Large-Scale Two-Level Networks. XVI Jornadas de Paralelismo, 2005.
M. Moreto, Martínez, C., Beivide, R., Vallejo, E., and Valero, M., Hierarchical Gaussian Topologies. ACACES 2005, Poster Abstracts. Advanced Computer Architecture and Compilation for Embedded Systems, 2005.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., Heterogeneity-Aware Architectures, XV Jornadas de Paralelismo. pp. 202-207, 2004.
M. Álvarez, Salami, E., Ramirez, A., and Valero, M., HD-VideoBench. A Benchmark for Evaluating High Definition Digital Video Applications, 2007 IEEE International Symposium on Workload Characterization (IISWC-2007). IEEE Computer Society Press, pp. 120-125, 2007.
C. Acosta, Falcón, A., Ramirez, A., and Valero, M., hdSMT: An Heterogeneity-Aware Simultaneous Multithreaded Architecture, XVI Jornadas de Paralelismo. pp. 59-66, 2005.
G. Kestor, Gioiosa, R., Unsal, O., Cristal, A., and Valero, M., Hardware/Software Techniques for Assisted Execution Runtime Systems, The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE). 2012.
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Hardware Transactional Memory with Operating System Support, HTMOS, in Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par, IRISA, Rennes, France, 2007.
M. Paolieri, Quiñones, E., Cazorla, F., Bernat, G., and Valero, M., Hardware Support for WCET Analysis of Multicore Systems. In International Symposium on Computer Architecture, Austin, USA, 2009.
T. Monreal, Viñals, V., González, A., and Valero, M., Hardware Support for Early Register Release. IJHPCN. International Journal on High Performance and Networking, 2005.
Q. Liu, Moreto, M., Jiménez, V., Abella, J., Cazorla, F. J., and Valero, M., Hardware Support for Accurate Per-task Energy Metering in Multicore Systems, ACM Trans. Archit. Code Optim., vol. 10. ACM, New York, NY, USA, pp. 34:1–34:27, 2013.
M. Moreto, Paolieri, M., Abella, J., Quiñones, E., Cazorla, F., and Valero, M., Hard Real-Time Capable Multicore Processors for Space Applications. ESTEC 1st Networking/Partnering Day, 2010.