Publications

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Rico, A. et al. Trace-driven simulation of multithreaded applications. 2011 IEEE International Symposium on Performance Analysis of Systems and Software 87--96 (2011).
Rico, A., Ramirez, A. & Valero, M. Trace Filtering of Multithreaded Applications for CMP Memory Simulation. IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013) 134–135 (2013).
Etsion, Y. et al. Task Superscalar: An Out-of-Order Task Pipeline. IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43) 89-100 (2010). at <http://dx.doi.org/10.1109/MICRO.2010.13>
Rico, A., Ramirez, A. & Valero, M. Task Management Analysis on the Cell BE. XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain) 271-276 (2008).
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Rico, A. et al. Performance and Power Evaluation of an In-line Accelerator. 2010 ACM International Conference on Computing Frontiers (2010).
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Cabarcas, F. et al. A module based Cell processor simulator. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) (2006).
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Rajovic, N. et al. Experiences With Mobile Processors for Energy Efficient HPC. ACM/IEEE Design, Automation, and Test in Europe (DATE) 464–468 (2013).
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Vega, A., Rico, A., Cabarcas, F., Ramirez, A. & Valero, M. Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
Cabarcas, F. et al. CellSim: A Validated Modular Heterogeneous Multiprocessor Simulator. XVIII Jornadas de Paralelismo de Zaragoza 181-188 (2007).
Cabarcas, F. et al. CellSim: A Cell Processor Simulation Infrastructure. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 279-282 (2007).