Publications

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A. Rico, Duran, A., Cabarcas, F., Etsion, Y., Ramirez, A., and Valero, M., Trace-driven simulation of multithreaded applications, 2011 IEEE International Symposium on Performance Analysis of Systems and Software. p. 87--96, 2011.
A. Rico, Ramirez, A., and Valero, M., Trace Filtering of Multithreaded Applications for CMP Memory Simulation, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013). Austin, United States, pp. 134–135, 2013.
N. Rajovic, Rico, A., Puzovic, N., Adeniyi-Jones, C., and Ramirez, A., Tibidabo: Making the case for an ARM-based HPC system, Future Generation Computer Systems, vol. 36. pp. 322–334, 2014.
N. Rajovic, Rico, A., Puzovic, N., Adeniyi-Jones, C., and Ramirez, A., Tibidabo: Making the case for an ARM-based HPC system, Future Generation Computer Systems, vol. 36. pp. 322–334, 2014.
Y. Etsion, Cabarcas, F., Rico, A., Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: An Out-of-Order Task Pipeline, IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43). pp. 89-100, 2010.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ramirez, A., Task Sampling: Computer Architecture Simulation in the Many-Core Era, Advanced Computer Architecture and Compilation for Embedded Systems (ACACES). 2014.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ramirez, A., Task Sampling: Computer Architecture Simulation in the Many-Core Era, in Advanced Computer Architecture and Compilation for for High-Performance and Embedded Systems, Fiuggi, Italy, 2014, pp. 165–168.
A. Rico, Ramirez, A., and Valero, M., Task Management Analysis on the Cell BE, XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain). pp. 271-276, 2008.
S
A. Rico, Cabarcas, F., Villavieja, C., Pavlovic, M., Vega, A., Etsion, Y., Ramirez, A., and Valero, M., On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels, ACM Transactions on Architecture and Code Optimization, vol. 8. p. 36, 2012.
U. Milic, Rico, A., and Ramirez, A., Sharing the Instruction Cache Among Multiple Cores for HPC Applications, in Advanced Computer Architecture and Compilation for for High-Performance and Embedded Systems, Fiuggi, Italy, 2014, pp. 69–72.
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F. Cabarcas, Rico, A., Ródenas, D., Martorell, X., Ramirez, A., and Ayguadé, E., A module based Cell processor simulator, 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). 2006.
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N. Rajovic, Rico, A., Vipond, J., Gelado, I., Puzovic, N., and Ramirez, A., Experiences With Mobile Processors for Energy Efficient HPC, ACM/IEEE Design, Automation, and Test in Europe (DATE). ACM, IEEE, Grenoble, France, pp. 464–468, 2013.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ramirez, A., Evaluating Execution Time Predictability of Task-Based Programs, in 7th International Workshop on Multi-/Many-Core Computing Systems, Porto, Portugal, 2014, pp. 218–229.
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A. Vega, Rico, A., Cabarcas, F., Ramirez, A., and Valero, M., Comparing last-level cache designs for CMP architectures, IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies. 2010.
F. Cabarcas, Rico, A., Ródenas, D., Martorell, X., Ramirez, A., and Ayguadé, E., CellSim: A Validated Modular Heterogeneous Multiprocessor Simulator, XVIII Jornadas de Paralelismo de Zaragoza. Zaragoza (Spain), pp. 181-188, 2007.
F. Cabarcas, Rico, A., Ródenas, D., Martorell, X., Ramirez, A., and Ayguadé, E., CellSim: A Cell Processor Simulation Infrastructure, 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07). pp. 279-282, 2007.