Publications

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2012
Rico, A., Cabarcas, F., Villavieja, C., Pavlovic, M., Vega, A., Etsion, Y., Ramirez, A. & Valero, M. On the Simulation of Large-scale Architectures Using Multiple Application Abstraction Levels. ACM Transactions on Architecture and Code Optimization 8, 36 (2012).
2011
Rico, A., Duran, A., Cabarcas, F., Etsion, Y., Ramirez, A. & Valero, M. Trace-driven simulation of multithreaded applications. 2011 IEEE International Symposium on Performance Analysis of Systems and Software 87--96 (2011).
2010
Vega, A., Rico, A., Cabarcas, F., Ramirez, A. & Valero, M. Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
Cabarcas, F., Rico, A., Etsion, Y. & Ramirez, A. Interleaving Granularity on High Bandwidth Memory Architecture for CMPs. Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS X) 250-257 (2010).at <http://dx.doi.org/10.1109/ICSAMOS.2010.5642060>
Rico, A., Derby, J.H., Montoye, R.K., Heil, T.H., Cher, C.-Y. & Bose, P. Performance and Power Evaluation of an In-line Accelerator. 2010 ACM International Conference on Computing Frontiers (2010).
Etsion, Y., Cabarcas, F., Rico, A., Ramirez, A., Badia, R.M., Ayguadé, E., Labarta, J. & Valero, M. Task Superscalar: An Out-of-Order Task Pipeline. IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43) 89-100 (2010).at <http://dx.doi.org/10.1109/MICRO.2010.13>
2009
Rico, A., Ramirez, A. & Valero, M. Available task-level parallelism on the Cell BE. Scientific Programming 17, 59-76 (2009).
2008
Rico, A., Ramirez, A. & Valero, M. Task Management Analysis on the Cell BE. XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain) 271-276 (2008).
2007
Cabarcas, F., Rico, A., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. CellSim: A Cell Processor Simulation Infrastructure. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 279-282 (2007).
Cabarcas, F., Rico, A., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. CellSim: A Validated Modular Heterogeneous Multiprocessor Simulator. XVIII Jornadas de Paralelismo de Zaragoza 181-188 (2007).
Rico, A., Cabarcas, F., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. Implementation and Validation of a Cell Simulator using UNISIM. 3rd HiPEAC Industrial Workshop (2007).
2006
Cabarcas, F., Rico, A., Ródenas, D., Martorell, X., Ramirez, A. & Ayguadé, E. A module based Cell processor simulator. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) (2006).