Publications

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2014
V. Garcia, Rico, A., Villavieja, C., Carpenter, P., Navarro, N., and Ramirez, A., Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors, Third International Workshop On-chip memory hierarchies and interconnects: organization, management and implementation. Springer International Publishing, Porto, Portugal, pp. 1888-1892, 2014.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ramirez, A., Evaluating Execution Time Predictability of Task-Based Programs, 7th International Workshop on Multi-/Many-Core Computing Systems. Springer International Publishing, Porto, Portugal, pp. 218–229, 2014.
U. Milic, Rico, A., and Ramirez, A., Sharing the Instruction Cache Among Multiple Cores for HPC Applications, Advanced Computer Architecture and Compilation for for High-Performance and Embedded Systems. Academic Press Ghent (Belgium), Fiuggi, Italy, pp. 69–72, 2014.
T. Grass, Rico, A., Casas, M., Moreto, M., and Ramirez, A., Task Sampling: Computer Architecture Simulation in the Many-Core Era, Advanced Computer Architecture and Compilation for for High-Performance and Embedded Systems. Academic Press Ghent (Belgium), Fiuggi, Italy, pp. 165–168, 2014.
N. Rajovic, Rico, A., Puzovic, N., Adeniyi-Jones, C., and Ramirez, A., Tibidabo: Making the case for an ARM-based HPC system, Future Generation Computer Systems, vol. 36. pp. 322–334, 2014.
2013
N. Rajovic, Rico, A., Vipond, J., Gelado, I., Puzovic, N., and Ramirez, A., Experiences With Mobile Processors for Energy Efficient HPC, ACM/IEEE Design, Automation, and Test in Europe (DATE). ACM, IEEE, Grenoble, France, pp. 464–468, 2013.
A. Rico, Raising the Level of Abstraction: Simulation of Large Chip Multiprocessors Running Multithreaded Applications, Universitat Politecnica de Catalunya (UPC), 2013.
A. Rico, Ramirez, A., and Valero, M., Trace Filtering of Multithreaded Applications for CMP Memory Simulation, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013). Austin, United States, pp. 134–135, 2013.
2011
A. Rico, Duran, A., Cabarcas, F., Etsion, Y., Ramirez, A., and Valero, M., Trace-driven simulation of multithreaded applications, 2011 IEEE International Symposium on Performance Analysis of Systems and Software. p. 87--96, 2011.
2010
A. Vega, Rico, A., Cabarcas, F., Ramirez, A., and Valero, M., Comparing last-level cache designs for CMP architectures, IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies. 2010.
F. Cabarcas, Rico, A., Etsion, Y., and Ramirez, A., Interleaving Granularity on High Bandwidth Memory Architecture for CMPs, Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS X). pp. 250-257, 2010.
A. Rico, Derby, J. H., Montoye, R. K., Heil, T. H., Cher, C. - Y., and Bose, P., Performance and Power Evaluation of an In-line Accelerator, 2010 ACM International Conference on Computing Frontiers. 2010.
Y. Etsion, Cabarcas, F., Rico, A., Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: An Out-of-Order Task Pipeline, IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43). pp. 89-100, 2010.
2009
A. Rico, Ramirez, A., and Valero, M., Available task-level parallelism on the Cell BE, Scientific Programming, vol. 17, no. 1-2. pp. 59-76, 2009.
2008
A. Rico, Ramirez, A., and Valero, M., Task Management Analysis on the Cell BE, XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain). pp. 271-276, 2008.
2006
F. Cabarcas, Rico, A., Ródenas, D., Martorell, X., Ramirez, A., and Ayguadé, E., A module based Cell processor simulator, 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06). 2006.