Publications

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Author Title Type [ Year(Asc)]
Filters: Author is Miquel Moreto  [Clear All Filters]
2014
Liu, Q., Moreto, M., Abella, J., Cazorla, F. J. & Valero, M. DReAM: Per-Task DRAM Energy Metering in Multicore Systems. Euro-Par 2014 Parallel Processing - 20th International Conference, Porto, Portugal, August 25-29, 2014. Proceedings 111–123 (2014). doi:10.1007/978-3-319-09873-9_10
Valero, M., Moreto, M., Casas, M., Ayguadé, E. & Labarta, J. Runtime-Aware Architectures: A First Approach. International Journal on Supercomputing Frontiers and Innovations 1, 29-44 (2014).
2013
Luque, C., Moreto, M., Cazorla, F. J. & Valero, M. Fair CPU Time Accounting in CMP+SMT Processors. ACM Trans. Archit. Code Optim. 9, 50:1–50:25 (2013).
Cook, H. et al. A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness. Proceedings of the 40th Annual International Symposium on Computer Architecture 308–319 (2013). doi:10.1145/2485922.2485949
Liu, Q. et al. Hardware Support for Accurate Per-task Energy Metering in Multicore Systems. ACM Trans. Archit. Code Optim. 10, 34:1–34:27 (2013).
Liu, Q. et al. Per-task Energy Accounting in Computing Systems. In IEEE Computer Architecture Letters (CAL) (2013). doi:http://people.ac.upc.edu/jabella/camerareadyIEEECAL.pdf‎
Camarero, C., Vallejo, E., Martinez, C., Moreto, M. & Beivide, R. Task Mapping in Rectangular Twisted Tori. Proceedings of the High Performance Computing Symposium 15:1–15:11 (2013). at <http://dl.acm.org/citation.cfm?id=2499968.2499983>
2007
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Explaining Dynamic Cache Partitioning Speed Ups. IEEE Computer Architecture Letters 6, 1-12 (2007).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. MLP-aware dynamic cache partitioning. International Conference on Parallel Architectures and Compilation Techniques (PACT) 418-418 (2007).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Online Prediction of Applications Cache Utility. International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS) 169-177 (2007).
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Online Prediction of Throughput for Different Cache Sizes. XVIII Jornadas de Paralelismo (2007).
2006
Moreto, M., Ramirez, A. & Valero, M. Reducing Simulation Time. 2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06) (2006).