Publications

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2008
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications. Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS'08) 53-64 (2008).
Álvarez, M., Ramirez, A., Martorell, X., Ayguadé, E. & Valero, M. Scalability of Macroblock-level Parallelism for H.264 Decoding. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008, Poster 59-62 (2008).
Rico, A., Ramirez, A. & Valero, M. Task Management Analysis on the Cell BE. XIX Jornadas de Paralelismo, pp. 271-276, Castellón (Spain) 271-276 (2008).
2009
Carpenter, P., Ramirez, A. & Ayguadé, E. The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. IX International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop IX) 12-23 (2009).
Rico, A., Ramirez, A. & Valero, M. Available task-level parallelism on the Cell BE. Scientific Programming 17, 59-76 (2009).
Bellens, P. et al. CellSs: Scheduling Techniques to Better Exploit Memory Hierarchy. (2009).
Etsion, Y., Ramirez, A., Badia, R. M. & Labarta, J. Cores as Functional Units: A Task-Based, Out-of-Order, Dataflow Pipeline. Advanced Computer Architecture and Compilation for Embedded Systems (ACACES) (2009).
Santana, O. J., Falcón, A., Ramirez, A. & Valero, M. DIA: A Complexity-Effective Decoding Architecture. IEEE Transactions on Computers 58, 448-462 (2009).
Sánchez, F., Ramirez, A. & Valero, M. Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem. 4CCC. 4th Colombian Computing Conference (2009).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 0163-5980 (2009).
Azevedo, A. et al. A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers 4, (2009).
Carpenter, P., Ramirez, A. & Ayguadé, E. Mapping stream programs onto heterogeneous multiprocessor systems. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2009) 57-66 (2009).
Azevedo, A. et al. Parallel H.264 Decoding on an Embedded Multicore Processor. 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'09) 404-418 (2009).
Meenderinck, C., Azevedo, A., Juurlink, B., Álvarez, M. & Ramirez, A. Parallel Scalability of Video Decoders. Journal of Signal Processing Systems 57, 173-194 (2009).
Álvarez, M. et al. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. Avances en Sistemas e Informática 6, 219-228 (2009).
Sánchez, F., Ramirez, A. & Valero, M. Quantitative analysis of sequence alignment applications on multiprocessor architectures. 6th ACM conference on Computing frontiers 61-70 (2009).
Álvarez, M., Ramirez, A., Meenderinck, C., Juurlink, B. & Valero, M. Scalability of Macroblock-level parallelism for H.264 decoding. The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09) (2009).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Thread to Core Assignment in SMT On-Chip Multiprocessors. 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09) (2009).
2010
Carpenter, P., Ramirez, A. & Ayguadé, E. Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors. International conference on High-Performance Embedded Architectures and Compilers (HiPEAC) 2010 96-110 (2010).
Pavlovic, M., Etsion, Y. & Ramirez, A. Can Manycores Support the Memory Requirements of Scientific Applications?. Workshop on Applications for Multi and Many Core Processors (A4MMC) (2010).
Vega, A., Rico, A., Cabarcas, F., Ramirez, A. & Valero, M. Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
Vujic, N. et al. DMA++: On the Fly Data Realignment for On-Chip Memories. 16th IEEE International Symposium on High-Performance Computer Architecture (2010).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 86-96 (2010).
Cabarcas, F., Rico, A., Etsion, Y. & Ramirez, A. Interleaving Granularity on High Bandwidth Memory Architecture for CMPs. Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS X) 250-257 (2010). at <http://dx.doi.org/10.1109/ICSAMOS.2010.5642060>
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Long DNA Sequence Comparison on Multicore Architectures. 16th international Euro-Par conference on Parallel processing (2010). at <http://dx.doi.org/10.1007/978-3-642-15291-7_24>
Álvarez, M. et al. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia) (2010).
Ramirez, A. et al. The SARC Architecture. IEEE Micro 30, 16-29 (2010).
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment in a Multicore. International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) (2010).
Isaza, S., Sánchez, F., Gaydadjiev, G. N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment on a Multicore. Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10) 889-894 (2010). at <http://dx.doi.org/10.1109/CISIS.2010.149>
Carpenter, P., Ramirez, A. & Ayguadé, E. Starsscheck: a tool to find errors in task-based parallel programs. 16th international Euro-Par conference on Parallel processing 2-13 (2010). at <http://portal.acm.org/citation.cfm?id=1887695.1887698>
Etsion, Y. et al. Task Superscalar: An Out-of-Order Task Pipeline. IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43) 89-100 (2010). at <http://dx.doi.org/10.1109/MICRO.2010.13>
Etsion, Y. et al. Task Superscalar: Using Processors as Functional Units. USENIX Workshop on Hot Topics In Parallelism (HotPar) (2010).
2012
Vujic, N. et al. DMA++: On the Fly Data Realignment for On-Chip Memories. Computers, IEEE Transactions on 61, 237 -250 (2012).
Göddeke, D. et al. Energy efficiency vs. performance of the numerical solution of PDEs: An application study on a low-power ARM-based cluster. Journal of Computational Physics 237, 132--150 (2012).
Ayguadé, E. et al. Programming Multi-Core and Many-Core Computing Systems (Wiley Series on Parallel and Distributed Computing) (John Wiley & Sons, Inc., 2012). at <http://www.par.univie.ac.at/~pllana/manycore_book/>
Radojkovic, P., Carpenter, P., Moreto, M., Ramirez, A. & Cazorla, F. Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem . International Symposium on Microarchitecture (MICRO-45) (2012).
Radojkovic, P., Carpenter, P., Moretó, M., Ramirez, A. & Cazorla, F. J. Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem. International Symposium on Microarchitecture (MICRO-45) (2012). at <http://capinfo.e.ac.upc.edu/PDFs/dir01/file004119.pdf>
González, S. et al. Prediction of regulatory regions using ReLA". 16th Annual International Conference on Research in Computational Molecular Biology. 16th Annual International Conference on Research in Computational Molecular Biology, RECOMB (2012).
González, S. et al. ReLA, a local alignment search tool for the identification of distal and proximal gene regulatory regions and their conserved transcription factor binding sites. Bioinformatics (2012). at <http://bioinformatics.oxfordjournals.org/content/28/6/763.long>
2013
Pavlovic, M., Puzovic, N. & Ramirez, A. Data placement in HPC architectures with heterogeneous off-chip memory. 31nd IEEE International Conference on Computer Design 193–200 (2013).
Rajovic, N. et al. Experiences With Mobile Processors for Energy Efficient HPC. ACM/IEEE Design, Automation, and Test in Europe (DATE) 464–468 (2013).
Rajovic, N., Vilanova, L., Villavieja, C., Puzovic, N. & Ramirez, A. The Low Power Architecture Approach Towards Exascale Computing. Journal of Computational Science 4, 439–443 (2013).
Rajovic, N., Puzovic, N., Vilanova, L., Villavieja, C. & Ramirez, A. The low-power architecture approach towards exascale computing. Journal of Computational Science (2013). doi:http://dx.doi.org/10.1016/j.jocs.2013.01.002
Milic, U., Gelado, I., Puzovic, N., Ramirez, A. & Tomasevic, M. Parallelizing general histogram application for CUDA architectures. 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII) 11–18 (2013). doi:10.1109/SAMOS.2013.6621100

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