Publications

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C
Seyedi, A. et al. Circuit Design of a Dual-Versioning L1 Data Cache. Integration The VLSI Journal (2011).
Sanyal, S., Roy, S., Cristal, A., Unsal, O. & Valero, M. Clock gate on abort: Towards energy-efficient hardware Transactional Memory. 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009) 1–8 (IEEE, 2009).
Milovanovic, M. et al. Compile time support for using transactional memory in C/C++ applications. The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11) 16–23 (2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003751.pdf>
D
Zyulkyarov, F., Harris, T., Unsal, O., Cristal, A. & Valero, M. Debugging Programs that use Atomic Blocks and Transactional Memory. 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2010) (2010).
Perfumo, C., Sönmez, N., Cristal, A., Unsal, O. & Valero, M. Development and Analysis of the Haskell Transactional Memory Benchmark Suite. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 139–140 (Academia Press, 2007).
Villavieja, C. et al. DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory. Parallel Architectures and Compilation Techniques (PACT) (2011).
Perfumo, C. et al. Dissecting Transactional Executions in Haskell. The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2007) (2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir17/file003700.pdf>
Harris, T., Tomić, S., Cristal, A. & Unsal, O. Dynamic Filtering: Multi-Purpose Architecture Support for Language Runtime Systems. 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'10) 39–52 (ACM, 2010).
Sanyal, S., Roy, S., Cristal, A., Unsal, O. & Valero, M. Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory. 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009 171–179 (IEEE, 2009).
M
Zyulkyarov, F. et al. Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors. Workshop on Operating System Support for Heterogeneous Multicore Architectures (2007).
Milovanovic, M. et al. Multithreaded software transactional memory and OpenMP. 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007) 81–88 (ACM, 2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003647.pdf>
N
Milovanovic, M. et al. Nebelung: Execution Environment for Transactional OpenMP. International Journal of Parallel Programming 36, 326–346 (2008).
S
Armejach, A. et al. ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. (2010).
Sönmez, N. et al. Software Transactional Memory Implementation. Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009) 101–103 (Academia Press, 2009).
Kestor, G. et al. STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems. The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT) (2011).
Zyulkyarov, F., Unsal, O., Cristal, A. & Valero, M. Synthetic Workloads for Transactional Memory. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 135–137 (Academia Press, 2007).
T
Sönmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009) 1–10 (IEEE, 2009).
Sonmez, N., Harris, T., Cristal, A., Unsal, O. & Valero, M. Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing 1–10 (2009). doi:10.1109/IPDPS.2009.5161032
Sonmez, N. et al. TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
Sonmez, N. et al. {TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
Vallejo, E. et al. Towards Fair Scalable Locking. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) (2008). at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003705.pdf>
Kestor, G., Unsal, O., Cristal, A. & Valero, M. Transactional Look-based Parallel Program. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 71–75 (HiPEAC Network of Excellence, 2008).
Harris, T. et al. Transactional Memory: An Overview. IEEE Micro 27, 8–29 (2007).
Milovanovic, M. et al. Transactional Memory and OpenMP. International Workshop on OpenMP (IWOMP-2007) 37–53 (Springer-Verlag, 2007). at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003195.pdf>
Hayes, T., Palomar, O., Unsal, O., Cristal, A. & Valero, M. True Vector Extensions for Decision Support DBMS Acceleration. (2011).
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. ACM SIGPLAN Notices 44, 307–308 (2009).
Kulkarni, C., Unsal, O., Cristal, A., Ayguadé, E. & Valero, M. Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 307–308 (ACM, 2009).