Publications

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A
E. Vallejo, Beivide, R., Cristal, A., Harris, T., Vallejo, F., Unsal, O., and Valero, M., Architectural Support for Fair Reader-Writer Locking, International Symposium on Microarchitecture. Atlanta, United States, 2010.
N. Markovic, González, R., Unsal, O., Valero, M., and Cristal, A., Architecture for Object-Oriented Programming Model. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2009.
F. Zyulkyarov, Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., Harris, T., and Valero, M., Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server, 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009). ACM, Raleigh, North Carolina, United States, pp. 25–34, 2009.
C
A. Seyedi, Armejach, A., Cristal, A., Unsal, O., Hur, I., and Valero, M., Circuit Design of a Dual-Versioning L1 Data Cache, Integration The VLSI Journal, 2011.
S. Sanyal, Roy, S., Cristal, A., Unsal, O., and Valero, M., Clock gate on abort: Towards energy-efficient hardware Transactional Memory, 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009). IEEE, Rome, Italy, pp. 1–8, 2009.
M. Milovanovic, Unsal, O., Cristal, A., Stipić, S., Zyulkyarov, F., and Valero, M., Compile time support for using transactional memory in C/C++ applications, The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11). Phoenix, AR, United States, pp. 16–23, 2007.
D
F. Zyulkyarov, Harris, T., Unsal, O., Cristal, A., and Valero, M., Debugging Programs that use Atomic Blocks and Transactional Memory, 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2010). Bangalore, India, 2010.
C. Perfumo, Sönmez, N., Cristal, A., Unsal, O., and Valero, M., Development and Analysis of the Haskell Transactional Memory Benchmark Suite, 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07). Academia Press, L'Aquila, Italy, pp. 139–140, 2007.
C. Villavieja, Karakostas, V., Vilanova, L., Etsion, Y., Ramirez, A., Mendelson, A., Navarro, N., Cristal, A., and Unsal, O., DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, 2011.
C. Perfumo, Sönmez, N., Unsal, O., Cristal, A., Harris, T., and Valero, M., Dissecting Transactional Executions in Haskell, The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2007). Portland, OR, United States, 2007.
T. Harris, Tomić, S., Cristal, A., and Unsal, O., Dynamic Filtering: Multi-Purpose Architecture Support for Language Runtime Systems, 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'10). ACM, Pittsburgh, PA, United States, pp. 39–52, 2010.
S. Sanyal, Roy, S., Cristal, A., Unsal, O., and Valero, M., Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory, 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009. IEEE, Seoul, South Korea, pp. 171–179, 2009.
H
S. Tomić, Cristal, A., Unsal, O., and Valero, M., Hardware Transactional Memory with Operating System Support, HTMOS, Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par. IRISA, Rennes, France, 2007.
G. Kestor, Gioiosa, R., Unsal, O., Cristal, A., and Valero, M., Hardware/Software Techniques for Assisted Execution Runtime Systems, The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE). 2012.
E. Vallejo, Harris, T., Cristal, A., Unsal, O., and Valero, M., Hybrid Transactional Memory to accelerate safe lock-based transactions, 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008). Salt Lake City, UT, United States, 2008.
M
F. Zyulkyarov, Unsal, O., Cristal, A., Milovanovic, M., Ayguadé, E., and Valero, M., Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors, Workshop on Operating System Support for Heterogeneous Multicore Architectures. Brasov, Romania, 2007.
M. Milovanovic, Ferrer, R., Gajinov, V., Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Multithreaded software transactional memory and OpenMP, 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007). ACM, Brasov, Romania, pp. 81–88, 2007.
P
N. Sönmez, Cristal, A., Unsal, O., Harris, T., and Valero, M., Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study, Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG 2009). Paphos, Cyprus, 2009.
Q
V. Gajinov, Zyulkyarov, F., Unsal, O., Cristal, A., Ayguadé, E., Harris, T., and Valero, M., QuakeTM: parallelizing a complex sequential application using transactional memory, 23rd international conference on Supercomputing (ICS 2009). ACM, Yorktown Heights, NY, United States, pp. 126–135, 2009.
R
V. Karakostas, Kestor, G., Unsal, O., Cristal, A., Hur, I., and Valero, M., RMS-TM: A challenging transactional memory benchmark suite, Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2010). Terrassa, Spain, 2010.
G. Kestor, Stipić, S., Unsal, O., Cristal, A., and Valero, M., RMS-TM: A Transactional Memory Benchmark for Recognition, Mining and Synthesis Applications, 4th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2009). Raleigh, NC, United States, 2009.
S
A. Armejach, Seyedi, A., Gil, R. T. J., Hur, I., Unsal, O., Cristal, A., and Valero, M., ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2010.
N. Sönmez, Perfumo, C., Stipić, S., Harris, T., Unsal, O., Cristal, A., and Valero, M., Software Transactional Memory Implementation, Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009). Academia Press, Terrassa, Spain, pp. 101–103, 2009.
G. Kestor, Gioiosa, R., Harris, T., Cristal, A., Unsal, O., Valero, M., and Hur, I., STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems, The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT). 2011.
F. Zyulkyarov, Unsal, O., Cristal, A., and Valero, M., Synthetic Workloads for Transactional Memory, 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07). Academia Press, L'Aquila, Italy, pp. 135–137, 2007.
T
N. Sönmez, Harris, T., Cristal, A., Unsal, O., and Valero, M., Taking the heat off transactions: Dynamic selection of pessimistic concurrency control, 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009). IEEE, Rome, Italy, pp. 1–10, 2009.
N. Sonmez, Harris, T., Cristal, A., Unsal, O., and Valero, M., Taking the heat off transactions: Dynamic selection of pessimistic concurrency control, Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing. IEEE Computer Society, Washington, DC, USA, pp. 1–10, 2009.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., {TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
N. Sonmez, Arcas, O., Pflucker, O., Unsal, O., Cristal, A., Hur, I., Singh, S., and Valero, M., TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System, Proc. FCCM '11. pp. 146–153, 2011.
E. Vallejo, Sanyal, S., Harris, T., Vallejo, F., Beivide, R., Unsal, O., Cristal, A., and Valero, M., Towards Fair Scalable Locking, Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008). Boston, MA, United States, 2008.
G. Kestor, Unsal, O., Cristal, A., and Valero, M., Transactional Look-based Parallel Program, Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008. HiPEAC Network of Excellence, L'Aquila, Italy, pp. 71–75, 2008.
T. Harris, Cristal, A., Unsal, O., Ayguadé, E., Galiardi, F., Smith, B., and Valero, M., Transactional Memory: An Overview, IEEE Micro, vol. 27, pp. 8–29, 2007.
M. Milovanovic, Ferrer, R., Unsal, O., Cristal, A., Martorell, X., Ayguadé, E., Labarta, J., and Valero, M., Transactional Memory and OpenMP, International Workshop on OpenMP (IWOMP-2007). Springer-Verlag, Beijing, China, pp. 37–53, 2007.
T. Hayes, Palomar, O., Unsal, O., Cristal, A., and Valero, M., True Vector Extensions for Decision Support DBMS Acceleration. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2011.
C. Kulkarni, Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions, ACM SIGPLAN Notices, vol. 44, pp. 307–308, 2009.
C. Kulkarni, Unsal, O., Cristal, A., Ayguadé, E., and Valero, M., Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions, 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009). ACM, Raleigh, North Carolina, United States, pp. 307–308, 2009.
U
N. Sönmez, Perfumo, C., Stipić, S., Unsal, O., Cristal, A., and Valero, M., UnreadTVar: Extending Haskell Software Transactional Memory for Performance, The 8th Symposium on Trends in Functional Programming (TFP 2007). New York, United States, pp. 1–11, 2007.
W
N. Sönmez, Cristal, A., Unsal, O., Harris, T., and Valero, M., Why you should profile Transactional Memory Applications on an Atomic Block basis: A Haskell Case Study. Departament d'Arquitectura de Computadors, Universitat Politècnica de Catalunya, 2008.
F. Zyulkyarov, Cristal, A., Cvijic, S., Ayguadé, E., Valero, M., Unsal, O., and Harris, T., WormBench: a configurable workload for evaluating transactional memory systems, 9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008). ACM, Toronto, Canada, pp. 61–68, 2008.