Publications
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Architectural Support for Fair Reader-Writer Locking. International Symposium on Microarchitecture (2010).
Architecture for Object-Oriented Programming Model. (2009).at <http://capinfo.e.ac.upc.edu/PDFs/dir11/file003491.pdf>
Atomic Quake: Using Transactional Memory in an Interactive Multiplayer Game Server. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 25–34 (2009).
Circuit Design of a Dual-Versioning L1 Data Cache. Integration The VLSI Journal (2011).
Clock gate on abort: Towards energy-efficient hardware Transactional Memory. 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009) 1–8 (2009).
Compile time support for using transactional memory in C/C++ applications. The 11th Annual Workshop on the Interaction between Compilers and Computer Architecture (INTERACT-11) 16–23 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir10/file003751.pdf>
Debugging Programs that use Atomic Blocks and Transactional Memory. 15th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP 2010) (2010).
Development and Analysis of the Haskell Transactional Memory Benchmark Suite. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 139–140 (2007).
DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory. Parallel Architectures and Compilation Techniques (PACT) (2011).
Dissecting Transactional Executions in Haskell. The Second ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2007) (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir17/file003700.pdf>
Dynamic Filtering: Multi-Purpose Architecture Support for Language Runtime Systems. 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'10) 39–52 (2010).
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory. 11th IEEE International Conference on High Performance Computing and Communications, HPCC 2009 171–179 (2009).
EazyHTM, Eager-Lazy Hardware Transactional Memory. 42nd International Symposium on Microarchitecture (MICRO) (2009).at <http://capinfo.e.ac.upc.edu/PDFs/dir07/file003458.pdf>
Extending C/C++ Language with Atomic Constructs. II Congreso Español de Informática (CEDI 2007) (2007).
FaulTM: Fault-Tolerance Using Hardware Transactional Memory. Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture (PESPMA) (2010).
Hardware Transactional Memory with Operating System Support, HTMOS. Workshop on Highly Parallel Processing on a Chip in conjunction with Euro-Par (2007).
Hardware/Software Techniques for Assisted Execution Runtime Systems. The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE) (2012).
Hybrid Transactional Memory to accelerate safe lock-based transactions. 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir16/file003699.pdf>
Increasing the Performance of Haskell Software Transactional Memory. II Congreso Español de Informática (CEDI 2007) (2007).
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment. 5th Conference on Computing Frontiers 67–78 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir06/file003457.pdf>
Memory Management for Transaction Processing Core in Heterogeneous Chip Multiprocessors. Workshop on Operating System Support for Heterogeneous Multicore Architectures (2007).
Multithreaded software transactional memory and OpenMP. 8th MEDEA Workshop Memory Performance: Dealing With Applications, Systems And Architecture (MEDEA 2007) 81–88 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003647.pdf>
Nebelung: Execution Environment for Transactional OpenMP. International Journal of Parallel Programming 36, 326–346 (2008).
Profiling Transactional Memory applications on an Atomic Block Basis: A Haskell case study. Second Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG 2009) (2009).
QuakeTM: parallelizing a complex sequential application using transactional memory. 23rd international conference on Supercomputing (ICS 2009) 126–135 (2009).at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file003443.pdf>
RMS-TM: A challenging transactional memory benchmark suite. Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2010) (2010).
RMS-TM: A Transactional Memory Benchmark for Recognition, Mining and Synthesis Applications. 4th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2009) (2009).at <http://capinfo.e.ac.upc.edu/PDFs/dir12/file003695.pdf>
ShadowHTM: Using a dual-bitcell L1 Data Cache to Improve Hardware Transactional Memory Performance. (2010).
Software Transactional Memory Implementation. Advanced Computer Architecture and Computation for Embedded Systems (ACACES 2009) 101–103 (2009).
STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems. The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT) (2011).
Synthetic Workloads for Transactional Memory. 2007 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-07) 135–137 (2007).
Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. 23rd IEEE International Symposium on Parallel {&} Distributed Processing (IPDPS 2009) 1–10 (2009).
Taking the heat off transactions: Dynamic selection of pessimistic concurrency control. Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing 1–10 (2009).doi:10.1109/IPDPS.2009.5161032
{TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System. Proc. FCCM '11 146–153 (2011).
Towards Fair Scalable Locking. Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM 2008) (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir22/file003705.pdf>
Transactional Look-based Parallel Program. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 71–75 (2008).
Transactional Memory and OpenMP. International Workshop on OpenMP (IWOMP-2007) 37–53 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir05/file003195.pdf>
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. ACM SIGPLAN Notices 44, 307–308 (2009).
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions. 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP 2009) 307–308 (2009).
UnreadTVar: Extending Haskell Software Transactional Memory for Performance. The 8th Symposium on Trends in Functional Programming (TFP 2007) 1–11 (2007).at <http://capinfo.e.ac.upc.edu/PDFs/dir12/file003753.pdf>
WormBench: a configurable workload for evaluating transactional memory systems. 9th workshop on MEmory performance: DEaling with Applications, systems and architecture (MEDEA 2008) 61–68 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir21/file003646.pdf>


