Publications

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A
Araya-Polo, M. et al. Assessing Accelerator-based HPC Reverse Time Migration. Transactions on Parallel and Distributed Systems, Special Issue on Accelerators 22(1), 147-162 (2011).
Dickov, B., Pericàs, M., Houzeaux, G., Navarro, N. & Ayguadé, E. Assessing the impact of network compression on Molecular Dynamics and Finite Element Methods. 14th International Conference on High-Performance Computing and Communications (HPCC-2012) (2012).
Gelado, I. et al. An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems. ACM SIGARCH Computer Architecture News - ASPLOS '10 (2010). at <http://doi.acm.org/10.1145/1735970.1736059>
H
Álvarez, L. et al. Hardware-software coherence protocol for the coexistence of caches and local memories. Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis 89:1–89:11 (2012). at <http://dl.acm.org/citation.cfm?id=2388996.2389117>
Alvarez, L. et al. Hardware-Software Coherence Protocol for the Coexistence of Caches and Local Memories. IEEE Transactions on Computers 99, 1 (2013).
Bosschere, K. D. et al. High Performance Embedded Architectures and Compilation Roadmap. (2007).
Cabezas, J., Araya-Polo, M., Gelado, I., Navarro, N. & Cela, J. M. High-Performance Reverse Time Migration on GPU. XXVIII International Conference of the Chilean Computer Society - XIII Workshop on Parallel and Distributed Systems (WSDP) (2009).
M
Gelado, I., Ramirez, A., Navarro, N. & Villavieja, C. Memory Management on Chip-MultiProcessors with on-chip Memories. Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA'08) 1-7 (2008).