Publications

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A
V. Garcia, Rico, A., Villavieja, C., Carpenter, P., Ramirez, A., and Navarro, N., Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors, OMHI Workshop 2014. 2014.
V. Garcia, Rico, A., Villavieja, C., Carpenter, P., Navarro, N., and Ramirez, A., Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors, in Third International Workshop On-chip memory hierarchies and interconnects: organization, management and implementation, Porto, Portugal, 2014.
B. Dickov, Pericas, M., Carpenter, P., Navarro, N., and Ayguadé, E., Analyzing performance improvements and energy savings in Infiniband Architecture using network compression, SBAC-PAD 2014. 2014.
B. Dickov, Pericas, M., Carpenter, P., Navarro, N., and Ayguadé, E., Analyzing performance improvements and energy savings in Infiniband Architecture using network compression, in International Symposium on Computer Architecture and High Performance Computing, Paris, France, 2014, pp. 73–80.
M. Araya-Polo, Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J. M., Ayguadé, E., Navarro, N., and Valero, M., Assessing Accelerator-based HPC Reverse Time Migration, Transactions on Parallel and Distributed Systems, Special Issue on Accelerators, vol. 22(1). pp. 147-162, 2011.
B. Dickov, Pericàs, M., Houzeaux, G., Navarro, N., and Ayguadé, E., Assessing the impact of network compression on Molecular Dynamics and Finite Element Methods, 14th International Conference on High-Performance Computing and Communications (HPCC-2012). Liverpool, UK, 2012.
I. Gelado, Stone, J. E., Cabezas, J., Patel, S., Navarro, N., and Hwu, W. -mei, An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems, ACM SIGARCH Computer Architecture News - ASPLOS '10. 2010.
J. Cabezas, Vilanova, L., Gelado, I., Jablin, T. B., Navarro, N., and Hwu, W. -meiW., Automatic execution of single-GPU computations across multiple GPUs, in 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT 2014), Edmonton, AB, Canada, 2014, pp. 467–468.
H
L. Álvarez, Vilanova, L., González, M., Martorell, X., Navarro, N., and Ayguadé, E., Hardware-software coherence protocol for the coexistence of caches and local memories, Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis. IEEE Computer Society Press, Los Alamitos, CA, USA, pp. 89:1–89:11, 2012.
L. Alvarez, Vilanova, L., Gonzalez, M., Martorell, X., Navarro, N., and Ayguade, E., Hardware-Software Coherence Protocol for the Coexistence of Caches and Local Memories, IEEE Transactions on Computers, vol. 99. IEEE Computer Society, Los Alamitos, CA, USA, p. 1, 2013.
K. D. Bosschere, Luk, W., Martorell, X., Navarro, N., O'Boyle, M., Pnevmatikatos, D., Ramirez, A., Sainrat, P., Seznec, A., Stenström, P., and Temam, O., High Performance Embedded Architectures and Compilation Roadmap. Transactions on HiPEAC Vol 1, Lecture Notes in Computer Science 4050, 2007.
J. Cabezas, Araya-Polo, M., Gelado, I., Navarro, N., and Cela, J. M., High-Performance Reverse Time Migration on GPU, XXVIII International Conference of the Chilean Computer Society - XIII Workshop on Parallel and Distributed Systems (WSDP). 2009.
M
I. Gelado, Ramirez, A., Navarro, N., and Villavieja, C., Memory Management on Chip-MultiProcessors with on-chip Memories, Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA'08). pp. 1-7, 2008.
P
T. Hussain, Navarro, N., Ayguadé, E., and Pericàs, M., PPMC : Hardware Scheduling and Memory Management Support for Multi Accelerators, 22nd International Conference on Field Programmable Logic and Applications (FPL-2012. Oslo, Norway, 2012.
V. J. Jiménez, Vilanova, L., Gelado, I., Gil, M., Fursin, G., and Navarro, N., Predictive Runtime Code Scheduling for Heterogeneous Architectures. Proc. of the 4th International Conference on High Performance Embedded Architectures and Compilers - HiPEAC '09, 2009.
T
M. Shafiq, Pericàs, M., Navarro, N., and Ayguadé, E., TARCAD: A template architecture for reconfigurable accelerator designs, IEEE Symposium on Application Specific Processors (SASP). pp. 8-15, 2011.
R. Giorgi, Badia, R. M., Bodin, F., Cohen, A., Evripidou, P., Faraboschi, P., Gao, G. R., Garbade, A., Gayatri, R., Girbal, S., Goodman, D., Koliai, S., Lujan, M., Mendelson, A., Morin, L., Navarro, N., Patejko, T., Pop, A., Trancoso, P., Ungerer, T., Watson, I., Weis, S., Zuckermann, S., and Valero, M., TERAFLUX: Harnessing dataflow in next generation teradevices, Microprocessors and Microsystems, vol. 38. pp. 976–990, 2014.
R. Giorgi, Badia, R. M., Bodin, F., Cohen, A., Evripidou, P., Faraboschi, P., Gao, G. R., Garbade, A., Gayatri, R., Girbal, S., Goodman, D., Koliai, S., Lujan, M., Mendelson, A., Morin, L., Navarro, N., Patejko, T., Pop, A., Trancoso, P., Ungerer, T., Watson, I., Weis, S., Zuckermann, S., and Valero, M., TERAFLUX: Harnessing dataflow in next generation teradevices, Microprocessors and Microsystems, vol. 38. pp. 976–990, 2014.
M. Solinas, Badia, R. M., Bodin, F., Cohen, A., Evripidou, P., Faraboschi, P., Navarro, N., and Valero, M., The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices, Euromicro Conference on Digital System Design, DSD 2013. IEEE Computer Society, Santander, Spain, pp. 272–279, 2013.