Publications

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2013
Rajovic, N., Puzovic, N., Vilanova, L., Villavieja, C. & Ramirez, A. The low-power architecture approach towards exascale computing. Journal of Computational Science (2013).doi:http://dx.doi.org/10.1016/j.jocs.2013.01.002
Saravanan, K.P., Carpenter, P. & Ramirez, A. Power/Performance evaluation of Energy Efficient Ethernet (EEE) for High Performance Computing. IEEE International Symposium on Performance Analysis of Systems and Software - ISPASS 2013 (2013).
Ciesko, J., Bueno, J., Puzovic, N., Ramirez, A., Badia, R.M. & Labarta, J. Programmable and Scalable Reductions on Clusters. Proceedings of 27th IEEE International Parallel and Distributed Processing Symposium (IEEE IPDPS) (2013).
2012
Vujic, N., Cabarcas, F., González, M., Ramirez, A., Martorell, X. & Ayguadé, E. DMA++: On the Fly Data Realignment for On-Chip Memories. Computers, IEEE Transactions on 61, 237 -250 (2012).
Göddeke, D., Komatitsch, D., Geveler, M., Ribbrock, D., Rajovic, N., Puzovic, N. & Ramirez, A. Energy efficiency vs. performance of the numerical solution of PDEs: An application study on a low-power ARM-based cluster. Journal of Computational Physics 237, 132--150 (2012).
Ayguadé, E., Badia, R.M., Bellens, P., Bueno-Hedo, J., Duran, A., Etsion, Y., Farreras, M., Ferrer, R., Labarta, J., Marjanovic, V., Martinell, L., Martorell, X., Pérez, J.M., Planas, J., Ramirez, A., Teruel, X., Tsalouchidou, I. & Valero, M. Hybrid/Heterogeneous Programming with OmpSs and its Software/Hardware Implications. Programming Multi-Core and Many-Core Computing Systems (Wiley Series on Parallel and Distributed Computing) (2012).at <http://www.par.univie.ac.at/~pllana/manycore_book/>
Radojkovic, P., Carpenter, P., Moreto, M., Ramirez, A. & Cazorla, F. Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem . International Symposium on Microarchitecture (MICRO-45) (2012).
Radojkovic, P., Carpenter, P., Moretó, M., Ramirez, A. & Cazorla, F.J. Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem. International Symposium on Microarchitecture (MICRO-45) (2012).at <http://capinfo.e.ac.upc.edu/PDFs/dir01/file004119.pdf>
González, S., Montserrat, B., Sánchez, F., Puiggros, M., Blanco, E., Martinez, L., Ramirez, A. & Torrents, D. Prediction of regulatory regions using ReLA". 16th Annual International Conference on Research in Computational Molecular Biology. 16th Annual International Conference on Research in Computational Molecular Biology, RECOMB (2012).
González, S., Montserrat, B., Sánchez, F., Puiggros, M., Blanco, E., Ramirez, A. & Torrents, D. ReLA, a local alignment search tool for the identification of distal and proximal gene regulatory regions and their conserved transcription factor binding sites. Bioinformatics (2012).at <http://bioinformatics.oxfordjournals.org/content/28/6/763.long>
2011
Carpenter, P., Ramirez, A. & Ayguadé, E. The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. Transactions on HiPEAC 5, (2011).
Villavieja, C., Karakostas, V., Vilanova, L., Etsion, Y., Ramirez, A., Mendelson, A., Navarro, N., Cristal, A. & Unsal, O. DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory. Parallel Architectures and Compilation Techniques (PACT) (2011).
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Parameterizing Multicore Architectures for Multiple Sequence Alignment. 2011 International Conference on Computing Frontiers (2011).
Ciobanu, C., Martorell, X., Kuzmanov, G.K., Ramirez, A. & Gaydadjiev, G.N. Scalability Evaluation of a Polymorphic Register File: A CG Case Study. Architecture of Computing Systems - ARCS 2011 13-25 (2011).doi:10.1007/978-3-642-19137-4.
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Scalable multicore architectures for long DNA sequence comparison. Concurrency and Computation Practice and Experience 23, (2011).
González, J., Giménez, J., Casas, M., Moretó, M., Ramirez, A., Labarta, J. & Valero, M. Simulating Whole Supercomputer Applications. IEEE Micro 31, 32-45 (2011).
2010
Carpenter, P., Ramirez, A. & Ayguadé, E. Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors. International conference on High-Performance Embedded Architectures and Compilers (HiPEAC) 2010 96-110 (2010).
Pavlovic, M., Etsion, Y. & Ramirez, A. Can Manycores Support the Memory Requirements of Scientific Applications?. Workshop on Applications for Multi and Many Core Processors (A4MMC) (2010).
Vega, A., Rico, A., Cabarcas, F., Ramirez, A. & Valero, M. Comparing last-level cache designs for CMP architectures. IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies (2010).
Vujic, N., González, M., Ayguadé, E., Martorell, X., Ramirez, A. & Cabarcas, F. DMA++: On the Fly Data Realignment for On-Chip Memories. 16th IEEE International Symposium on High-Performance Computer Architecture (2010).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 86-96 (2010).
Cabarcas, F., Rico, A., Etsion, Y. & Ramirez, A. Interleaving Granularity on High Bandwidth Memory Architecture for CMPs. Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS X) 250-257 (2010).at <http://dx.doi.org/10.1109/ICSAMOS.2010.5642060>
Sánchez, F., Cabarcas, F., Ramirez, A. & Valero, M. Long DNA Sequence Comparison on Multicore Architectures. 16th international Euro-Par conference on Parallel processing (2010).at <http://dx.doi.org/10.1007/978-3-642-15291-7_24>
Álvarez, M., Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C. & Juurlink, B. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia) (2010).
Ramirez, A., Cabarcas, F., Juurlink, B., Mesa, M.A., Sánchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S. & Gaydadjiev, G.N. The SARC Architecture. IEEE Micro 30, 16-29 (2010).
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment in a Multicore. International Workshop on Multi-Core Computing Systems (MuCoCoS 2010) (2010).
Isaza, S., Sánchez, F., Gaydadjiev, G.N., Ramirez, A. & Valero, M. Scalability Analysis of Progressive Alignment on a Multicore. Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10) 889-894 (2010).at <http://dx.doi.org/10.1109/CISIS.2010.149>
Carpenter, P., Ramirez, A. & Ayguadé, E. Starsscheck: a tool to find errors in task-based parallel programs. 16th international Euro-Par conference on Parallel processing 2-13 (2010).at <http://portal.acm.org/citation.cfm?id=1887695.1887698>
Etsion, Y., Cabarcas, F., Rico, A., Ramirez, A., Badia, R.M., Ayguadé, E., Labarta, J. & Valero, M. Task Superscalar: An Out-of-Order Task Pipeline. IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43) 89-100 (2010).at <http://dx.doi.org/10.1109/MICRO.2010.13>
Etsion, Y., Ramirez, A., Badia, R.M., Ayguadé, E., Labarta, J. & Valero, M. Task Superscalar: Using Processors as Functional Units. USENIX Workshop on Hot Topics In Parallelism (HotPar) (2010).
2009
Carpenter, P., Ramirez, A. & Ayguadé, E. The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors. IX International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop IX) 12-23 (2009).
Rico, A., Ramirez, A. & Valero, M. Available task-level parallelism on the Cell BE. Scientific Programming 17, 59-76 (2009).
Bellens, P., Pérez, J.M., Cabarcas, F., Ramirez, A., Badia, R.M. & Labarta, J. CellSs: Scheduling Techniques to Better Exploit Memory Hierarchy. (2009).
Etsion, Y., Ramirez, A., Badia, R.M. & Labarta, J. Cores as Functional Units: A Task-Based, Out-of-Order, Dataflow Pipeline. Advanced Computer Architecture and Compilation for Embedded Systems (ACACES) (2009).
Santana, O.J., Falcón, A., Ramirez, A. & Valero, M. DIA: A Complexity-Effective Decoding Architecture. IEEE Transactions on Computers 58, 448-462 (2009).
Sánchez, F., Ramirez, A. & Valero, M. Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem. 4CCC. 4th Colombian Computing Conference (2009).
Moreto, M., Cazorla, F., Ramirez, A., Sakellariou, R. & Valero, M. FlexDCP: a QoS framework for CMP architectures. ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors 43, 0163-5980 (2009).
Azevedo, A., Meenderinck, C., Juurlink, B., Tereckho, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A. & Valero, M. A Highly Scalable Parallel Implementation of H.264. Transactions on High-Performance Embedded Architectures and Compilers 4, (2009).
Carpenter, P., Ramirez, A. & Ayguadé, E. Mapping stream programs onto heterogeneous multiprocessor systems. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2009) 57-66 (2009).
Azevedo, A., Meenderinck, C., Juurlink, B., Terechko, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A. & Valero, M. Parallel H.264 Decoding on an Embedded Multicore Processor. 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'09) 404-418 (2009).
Meenderinck, C., Azevedo, A., Juurlink, B., Álvarez, M. & Ramirez, A. Parallel Scalability of Video Decoders. Journal of Signal Processing Systems 57, 173-194 (2009).
Álvarez, M., Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C. & Juurlink, B. Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture. Avances en Sistemas e Informática 6, 219-228 (2009).
Sánchez, F., Ramirez, A. & Valero, M. Quantitative analysis of sequence alignment applications on multiprocessor architectures. 6th ACM conference on Computing frontiers 61-70 (2009).
Álvarez, M., Ramirez, A., Meenderinck, C., Juurlink, B. & Valero, M. Scalability of Macroblock-level parallelism for H.264 decoding. The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09) (2009).
Acosta, C., Cazorla, F., Ramirez, A. & Valero, M. Thread to Core Assignment in SMT On-Chip Multiprocessors. 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09) (2009).
2008
Vega, A., Ramirez, A. & Valero, M. 3D Die-Stacking Architectures: State of the Art. Advanced Computer Architecture and Compilation for Embedded Systems. ACACES 2008 203-207 (2008).
Azevedo, A., Meenderinck, C., Juurlink, B., Álvarez, M. & Ramirez, A. Analysis of Video Filtering on the Cell Processor. 2008 IEEE International Symposium on Circuits and Systems (ISCAS'08) 488-491 (2008).
González, I., Galluzzi, M., Veidenbaum, A., Ramirez, A., Cristal, A. & Valero, M. A distributed processor state management architecture for large-window processors. 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41) 11–22 (2008).at <http://capinfo.e.ac.upc.edu/PDFs/dir14/file003697.pdf>
Moreto, M., Cazorla, F., Ramirez, A. & Valero, M. Dynamic Cache Partitioning Based on the MLP on Cache Misses. Transactions on HiPEAC 3, 1-21 (2008).
Gelado, I., Ramirez, A., Navarro, N. & Villavieja, C. Memory Management on Chip-MultiProcessors with on-chip Memories. Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA'08) 1-7 (2008).

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