Publications

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2013
M. Pavlovic, Puzovic, N., and Ramirez, A., Data placement in HPC architectures with heterogeneous off-chip memory, 31nd IEEE International Conference on Computer Design. Asheville, NC, United States, pp. 193–200, 2013.
N. Rajovic, Rico, A., Vipond, J., Gelado, I., Puzovic, N., and Ramirez, A., Experiences With Mobile Processors for Energy Efficient HPC, ACM/IEEE Design, Automation, and Test in Europe (DATE). ACM, IEEE, Grenoble, France, pp. 464–468, 2013.
N. Rajovic, Vilanova, L., Villavieja, C., Puzovic, N., and Ramirez, A., The Low Power Architecture Approach Towards Exascale Computing, Journal of Computational Science, vol. 4. pp. 439–443, 2013.
N. Rajovic, Puzovic, N., Vilanova, L., Villavieja, C., and Ramirez, A., The low-power architecture approach towards exascale computing, Journal of Computational Science. 2013.
U. Milic, Gelado, I., Puzovic, N., Ramirez, A., and Tomasevic, M., Parallelizing general histogram application for CUDA architectures, 2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII). Samos, Greece, pp. 11–18, 2013.
S. Karthikeyan, Carpenter, P., and Ramirez, A., Power/Performance evaluation of Energy Efficient Ethernet (EEE) for High Performance Computing, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013). Austin, United States, 2013.
J. Ciesko, Bueno-Hedo, J., Puzovic, N., Ramirez, A., Badia, R. M., and Labarta, J., Programmable and Scalable Reductions on Clusters, The 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013). IEEE, Boston, United States, pp. 560–568, 2013.
N. Rajovic, Carpenter, P., Gelado, I., Puzovic, N., Ramirez, A., and Valero, M., Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?, SC13: International Conference for High Performance Computing, Networking, Storage and Analysis. Denver, United States, pp. 40–40, 2013.
A. Rico, Ramirez, A., and Valero, M., Trace Filtering of Multithreaded Applications for CMP Memory Simulation, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013). Austin, United States, pp. 134–135, 2013.
2012
N. Vujic, Cabarcas, F., González, M., Ramirez, A., Martorell, X., and Ayguadé, E., DMA++: On the Fly Data Realignment for On-Chip Memories, Computers, IEEE Transactions on, vol. 61. pp. 237 -250, 2012.
D. Göddeke, Komatitsch, D., Geveler, M., Ribbrock, D., Rajovic, N., Puzovic, N., and Ramirez, A., Energy efficiency vs. performance of the numerical solution of PDEs: An application study on a low-power ARM-based cluster, Journal of Computational Physics, vol. 237. p. 132--150, 2012.
E. Ayguadé, Badia, R. M., Bellens, P., Bueno-Hedo, J., Duran, A., Etsion, Y., Farreras, M., Ferrer, R., Labarta, J., Marjanovic, V., Martinell, L., Martorell, X., Pérez, J. M., Planas, J., Ramirez, A., Teruel, X., Tsalouchidou, I., and Valero, M., Hybrid/Heterogeneous Programming with OmpSs and its Software/Hardware Implications, in Programming Multi-Core and Many-Core Computing Systems (Wiley Series on Parallel and Distributed Computing) , Wiley Series on "Parallel and Distributed Computing"., John Wiley & Sons, Inc., 2012.
P. Radojkovic, Carpenter, P., Moreto, M., Ramirez, A., and Cazorla, F., Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem, International Symposium on Microarchitecture (MICRO-45). 2012.
S. González, Montserrat, B., Sánchez, F., Puiggros, M., Blanco, E., Martinez, L., Ramirez, A., and Torrents, D., Prediction of regulatory regions using ReLA". 16th Annual International Conference on Research in Computational Molecular Biology, 16th Annual International Conference on Research in Computational Molecular Biology, RECOMB. 2012.
S. González, Montserrat, B., Sánchez, F., Puiggros, M., Blanco, E., Ramirez, A., and Torrents, D., ReLA, a local alignment search tool for the identification of distal and proximal gene regulatory regions and their conserved transcription factor binding sites, Bioinformatics. 2012.
2011
P. Carpenter, Ramirez, A., and Ayguadé, E., The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors, Transactions on HiPEAC, vol. 5, no. 3. 2011.
C. Villavieja, Karakostas, V., Vilanova, L., Etsion, Y., Ramirez, A., Mendelson, A., Navarro, N., Cristal, A., and Unsal, O., DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, 2011.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Parameterizing Multicore Architectures for Multiple Sequence Alignment, 2011 International Conference on Computing Frontiers. 2011.
C. Ciobanu, Martorell, X., Kuzmanov, G. K., Ramirez, A., and Gaydadjiev, G. N., Scalability Evaluation of a Polymorphic Register File: A CG Case Study, Architecture of Computing Systems - ARCS 2011. Springer-Verlag Berlin Heidelberg, pp. 13-25, 2011.
F. Sánchez, Cabarcas, F., Ramirez, A., and Valero, M., Scalable multicore architectures for long DNA sequence comparison, Concurrency and Computation Practice and Experience, vol. 23, no. 17. 2011.
J. González, Giménez, J., Casas, M., Moretó, M., Ramirez, A., Labarta, J., and Valero, M., Simulating Whole Supercomputer Applications, IEEE Micro, vol. 31. IEEE, pp. 32-45, 2011.
2010
P. Carpenter, Ramirez, A., and Ayguadé, E., Buffer sizing for self-timed stream programs on heterogeneous distributed memory multiprocessors, International conference on High-Performance Embedded Architectures and Compilers (HiPEAC) 2010. Pisa (Italy), pp. 96-110, 2010.
M. Pavlovic, Etsion, Y., and Ramirez, A., Can Manycores Support the Memory Requirements of Scientific Applications?, Workshop on Applications for Multi and Many Core Processors (A4MMC). 2010.
A. Vega, Rico, A., Cabarcas, F., Ramirez, A., and Valero, M., Comparing last-level cache designs for CMP architectures, IFMT '10: International Forum on Next-Generation Multicore/Manycore Technologies. 2010.
N. Vujic, González, M., Ayguadé, E., Martorell, X., Ramirez, A., and Cabarcas, F., DMA++: On the Fly Data Realignment for On-Chip Memories, 16th IEEE International Symposium on High-Performance Computer Architecture. Bangalore (India), 2010.
M. Moreto, Cazorla, F., Ramirez, A., Sakellariou, R., and Valero, M., FlexDCP: a QoS framework for CMP architectures, ACM Operating Systems Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, vol. 43, no. 2. pp. 86-96, 2010.
F. Cabarcas, Rico, A., Etsion, Y., and Ramirez, A., Interleaving Granularity on High Bandwidth Memory Architecture for CMPs, Intl. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS X). pp. 250-257, 2010.
F. Sánchez, Cabarcas, F., Ramirez, A., and Valero, M., Long DNA Sequence Comparison on Multicore Architectures, 16th international Euro-Par conference on Parallel processing. 2010.
M. Álvarez, Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C., and Juurlink, B., Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture, 4CCC. 4th Colombian Computing Conference, Bucaramanga (Colombia). 2010.
A. Ramirez, Cabarcas, F., Juurlink, B., Mesa, M. A., Sánchez, F., Azevedo, A., Meenderinck, C., Ciobanu, C., Isaza, S., and Gaydadjiev, G. N., The SARC Architecture, IEEE Micro, vol. 30, no. 5. pp. 16-29, 2010.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Scalability Analysis of Progressive Alignment in a Multicore, International Workshop on Multi-Core Computing Systems (MuCoCoS 2010). Krakow (Poland), 2010.
S. Isaza, Sánchez, F., Gaydadjiev, G. N., Ramirez, A., and Valero, M., Scalability Analysis of Progressive Alignment on a Multicore, Fourth International Conference on Complex, Intelligent and Software Intensive Systems (CISIS '10). pp. 889-894, 2010.
P. Carpenter, Ramirez, A., and Ayguadé, E., Starsscheck: a tool to find errors in task-based parallel programs, 16th international Euro-Par conference on Parallel processing. pp. 2-13, 2010.
Y. Etsion, Cabarcas, F., Rico, A., Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: An Out-of-Order Task Pipeline, IEEE/ACM Intl. Symp. on Microarchitecture (MICRO-43). pp. 89-100, 2010.
Y. Etsion, Ramirez, A., Badia, R. M., Ayguadé, E., Labarta, J., and Valero, M., Task Superscalar: Using Processors as Functional Units, USENIX Workshop on Hot Topics In Parallelism (HotPar). 2010.
2009
P. Carpenter, Ramirez, A., and Ayguadé, E., The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors, IX International Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS Workshop IX) . Samos (Greece), pp. 12-23, 2009.
A. Rico, Ramirez, A., and Valero, M., Available task-level parallelism on the Cell BE, Scientific Programming, vol. 17, no. 1-2. pp. 59-76, 2009.
P. Bellens, Pérez, J. M., Cabarcas, F., Ramirez, A., Badia, R. M., and Labarta, J., CellSs: Scheduling Techniques to Better Exploit Memory Hierarchy. Scientific Programming, vol 17, pp. 77-95, 2009.
Y. Etsion, Ramirez, A., Badia, R. M., and Labarta, J., Cores as Functional Units: A Task-Based, Out-of-Order, Dataflow Pipeline, Advanced Computer Architecture and Compilation for Embedded Systems (ACACES). 2009.
O. J. Santana, Falcón, A., Ramirez, A., and Valero, M., DIA: A Complexity-Effective Decoding Architecture, IEEE Transactions on Computers, vol. 58, no. 4. pp. 448-462, 2009.
F. Sánchez, Ramirez, A., and Valero, M., Exploiting Different Levels of Parallelism in the Biological Sequence Comparison Problem, 4CCC. 4th Colombian Computing Conference. Bucaramanga (Colombia), 2009.
M. Moreto, Cazorla, F., Ramirez, A., Sakellariou, R., and Valero, M., FlexDCP: a QoS framework for CMP architectures, ACM SIGOPS Operating System Review, Special Issue on the Interaction among the OS, Compilers, and Multicore Processors, vol. 43, no. 2. pp. 0163-5980, 2009.
A. Azevedo, Meenderinck, C., Juurlink, B., Tereckho, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A., and Valero, M., A Highly Scalable Parallel Implementation of H.264, Transactions on High-Performance Embedded Architectures and Compilers, vol. 4, no. 2. 2009.
P. Carpenter, Ramirez, A., and Ayguadé, E., Mapping stream programs onto heterogeneous multiprocessor systems, International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2009). Grenoble (France), pp. 57-66, 2009.
A. Azevedo, Meenderinck, C., Juurlink, B., Terechko, A., Hoogerbrugge, J., Álvarez, M., Ramirez, A., and Valero, M., Parallel H.264 Decoding on an Embedded Multicore Processor, 4th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC'09). pp. 404-418, 2009.
C. Meenderinck, Azevedo, A., Juurlink, B., Álvarez, M., and Ramirez, A., Parallel Scalability of Video Decoders, Journal of Signal Processing Systems, vol. 57, no. 2. pp. 173-194, 2009.
M. Álvarez, Ramirez, A., Valero, M., Azevedo, A., Meenderinck, C., and Juurlink, B., Performance Evaluation of Macroblock-level Parallelization of H.264 Decoding on a cc-NUMA Multiprocessor Architecture, Avances en Sistemas e Informática, vol. 6, no. 1. pp. 219-228, 2009.
F. Sánchez, Ramirez, A., and Valero, M., Quantitative analysis of sequence alignment applications on multiprocessor architectures, 6th ACM conference on Computing frontiers. Ischia (Italy), pp. 61-70, 2009.
M. Álvarez, Ramirez, A., Meenderinck, C., Juurlink, B., and Valero, M., Scalability of Macroblock-level parallelism for H.264 decoding, The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09). Shenzhen (China), 2009.
C. Acosta, Cazorla, F., Ramirez, A., and Valero, M., Thread to Core Assignment in SMT On-Chip Multiprocessors, 21st International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'09). 2009.

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