Mateo Valero Cortes

2014

• TERAFLUX: Harnessing dataflow in next generation teradevices

  Microprocessors and Microsystems

  R. Giorgi, R. M. Badia, F. Bodin, A. Cohen, P. Evripidou, P. Faraboschi, G. R. Gao, A. Garbade, R. Gayatri, S. Girbal, D. Goodman, S. Koliai, M. Lujan, A. Mendelson, L. Morin, N. Navarro, T. Patejko, A. Pop, P. Trancoso, T. Ungerer, I. Watson, S. Weis, S. Zuckermann, and M. Valero
• Thread Lock Section-aware Scheduling on Asymmetric Single-ISA Multi-Core

  IEEE Computer Architecture Letters

  N. Markovic, D. Nemirovsky, O. Unsal, M. Valero, and A. Cristal
• Using Dynamic Runtime Testing for Rapid Development of Architectural Simulators

  International Journal of Parallel Programming

  S. Tomić, A. Cristal, O. Unsal, and M. Valero
• Automatic Exploration of Potential Parallelism in Sequential Applications

  29th International Supercomputing Conference, ISC 2014

  V. Subotic, E. Ayguade, J. Labarta, and M. Valero
• Profile-Guided Transaction Coalescing—Lowering Transactional Overheads by Merging Transactions

  ACM Transactions on Architecture and Code Optimization 2014

  S. Stipic, V. Smiljkovi, O. Unsal, A. Cristal, and M. Valero
• PAMS: Pattern Aware Memory System for Embedded Systems

  ReConFig - International Conference on ReConFifurable Computing and FPGAs

  T. Hussain, N. Sönmez, O. Palomar, O. Unsal, A. Cristal, E. Ayguade, and M. Valero
• AMMC: Advanced Multi-core Memory Controller

  13th International Conference on Field Programmable Technology (FPT 2014)

  T. Hussain, O. Palomar, A. Cristal, O. Unsal, E. Ayguade, and M. Valero
• Dynamic Transaction Coalesing

  ACM International Conference on Computing Frontiers

  S. Stipic, V. Karakostas, V. Smiljkovi, V. Gajinov, O. Unsal, A. Cristal, and M. Valero
• Evaluation of vectorization potential of Graph500 on Intels Xeon Phi

  International Conference on High Performance Computing {&} Simulation, HPCS 2014

  Milan Stanic, O. Palomar, Ivan Ratkovic, M. Duric, O. Unsal, A. Cristal, and M. Valero
• DeTrans: Deterministic and Parallel execution of Transactions

  International Symposium on Computer Architecture and High Performance Computing

  V. Smiljkovi, S. Stipic, C. Fetzer, O. Unsal, A. Cristal, and M. Valero