NAVARRO, NACHO

2014
V. Garcia, Rico, A., Villavieja, C., Carpenter, P., Navarro, N., and Ramirez, A., Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors, Third International Workshop On-chip memory hierarchies and interconnects: organization, management and implementation. Springer International Publishing, Porto, Portugal, pp. 1888-1892, 2014.
B. Dickov, Pericas, M., Carpenter, P., Navarro, N., and Ayguadé, E., Analyzing performance improvements and energy savings in Infiniband Architecture using network compression, International Symposium on Computer Architecture and High Performance Computing. IEEE Press, Paris, France, pp. 73–80, 2014.
J. Cabezas, Vilanova, L., Gelado, I., Jablin, T. B., Navarro, N., and Hwu, W. -meiW., Automatic execution of single-GPU computations across multiple GPUs, 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT 2014). ACM, Edmonton, AB, Canada, pp. 467–468, 2014.
L. Vilanova, Ben-Yehuda, M., Navarro, N., Etsion, Y., and Valero, M., CODOMs: Protecting Software with Code-centric Memory Domains, 41st International Symposium on Computer Architecture (ISCA). Minneapolis, MN, United States, 2014.
I. Tanasic, Gelado, I., Cabezas, J., Ramirez, A., Navarro, N., and Valero, M., Enabling Preemptive Multiprogramming on GPUs, 41st International Symposium on Computer Architecture (ISCA). Minneapolis, MN, United States, 2014.
G. Lluis, Velasco, L., Navarro, N., and Junyent, G., Experimental assessment of a high performance back-end PCE for Flexgrid optical network re-optimization, OFC/NFOEC 2014 - Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference 2014. San Francisco, United States, pp. 1–3, 2014.
J. Cabezas, Gelado, I., Stone, J. E., Navarro, N., Kirk, D. B., and Hwu, W. -meiW., Runtime and Architecture Support for Efficient Data Exchange in Multi-Accelerator Applications, IEEE Transactions on Parallel and Distributed Systems, vol. 25. 2014.
B. Dickov, Pericas, M., Carpenter, P., Navarro, N., and Ayguadé, E., Software-Managed Power Reduction in Infiniband Links, 2014 International Conference on Parallel Processing (ICPP-2014). 2014.
R. Giorgi, Badia, R. M., Bodin, F., Cohen, A., Evripidou, P., Faraboschi, P., Gao, G. R., Garbade, A., Gayatri, R., Girbal, S., Goodman, D., Koliai, S., Lujan, M., Mendelson, A., Morin, L., Navarro, N., Patejko, T., Pop, A., Trancoso, P., Ungerer, T., Watson, I., Weis, S., Zuckermann, S., and Valero, M., TERAFLUX: Harnessing dataflow in next generation teradevices, Microprocessors and Microsystems, vol. 38. pp. 976–990, 2014.
2013
I. Tanasic, Vilanova, L., Jorda, M., Cabezas, J., Gelado, I., Navarro, N., and Hwu, W. -meiW., Comparison Based Sorting for Systems with Multiple GPUs, GPGPU-6 - Six Workshop on General Purpose Processing Using GPUs. Houston, TX, United States, 2013.
R. Bertran, González, M., Martorell, X., Navarro, N., and Ayguadé, E., Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up, Computer Journal, vol. 56. pp. 198–213, 2013.
L. Alvarez, Vilanova, L., Gonzalez, M., Martorell, X., Navarro, N., and Ayguadé, E., Hardware-Software Coherence Protocol for the Coexistence of Caches and Local Memories, IEEE Transactions on Computers, vol. 99. IEEE Computer Society, Los Alamitos, CA, USA, p. 1, 2013.
R. Bertran, Gonzalez, M., Martorell, X., Navarro, N., and Ayguadé, E., A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs, IEEE Transactions on Computers, vol. 62. IEEE Computer Society, Los Alamitos, CA, USA, pp. 1289-1302, 2013.
M. Solinas, Badia, R. M., Bodin, F., Cohen, A., Evripidou, P., Faraboschi, P., Navarro, N., and Valero, M., The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices, Euromicro Conference on Digital System Design, DSD 2013. IEEE Computer Society, Santander, Spain, pp. 272–279, 2013.
2012
B. Dickov, Pericàs, M., Houzeaux, G., Navarro, N., and Ayguadé, E., Assessing the impact of network compression on Molecular Dynamics and Finite Element Methods, 14th International Conference on High-Performance Computing and Communications (HPCC-2012). Liverpool, UK, 2012.
M. Shafiq, Pericàs, M., Navarro, N., and Ayguadé, E., BSArc: Blacksmith Streaming Architecture for HPC Accelerators, ACM International Conference on Computing Frontiers. Cagliary (Italy), 2012.
R. Bertran, González, M., Martorell, X., Navarro, N., and Ayguadé, E., Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up, The Computer Journal. 2012.
R. Bertran, Becerra, Y., Carrera, D., n, V. Ã. § B., González, M., Martorell, X., Navarro, N., Torres, J., and Ayguadé, E., Energy accounting for shared virtualized environments under DVFS using PMC-based power models, Future Generation Computer Systems, vol. 28. Elsevier, pp. 457 - 468, 2012.
L. Álvarez, Vilanova, L., González, M., Martorell, X., Navarro, N., and Ayguadé, E., Hardware-software coherence protocol for the coexistence of caches and local memories, Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis. IEEE Computer Society Press, Los Alamitos, CA, USA, pp. 89:1–89:11, 2012.
T. Hussain, Navarro, N., Ayguadé, E., and Pericàs, M., PPMC : Hardware Scheduling and Memory Management Support for Multi Accelerators, 22nd International Conference on Field Programmable Logic and Applications (FPL-2012. Oslo, Norway, 2012.
2011
M. Araya-Polo, Cabezas, J., Hanzich, M., Pericas, M., Morancho, E., Gelado, I., Shafiq, M., Rubio, F., Cela, J. M., Ayguadé, E., Navarro, N., and Valero, M., Assessing Accelerator-based HPC Reverse Time Migration, Transactions on Parallel and Distributed Systems, Special Issue on Accelerators, vol. 22(1). pp. 147-162, 2011.
L. Álvarez, Bertran, R., González, M., Martorell, X., Navarro, N., and Ayguadé, E., Design space exploration for aggressive core replication schemes in CMPs, Proceedings of the 20th international symposium on High performance distributed computing. ACM, New York, NY, USA, pp. 269–270, 2011.
C. Villavieja, Karakostas, V., Vilanova, L., Etsion, Y., Ramirez, A., Mendelson, A., Navarro, N., Cristal, A., and Unsal, O., DiDi: Mitigating The Performance Impact of TLB Shootdowns Using A Shared TLB Directory, Parallel Architectures and Compilation Techniques (PACT). Galveston Island, United States, 2011.
R. Bertran, Becerra, Y., Carrera, D., Beltran, V., González, M., Martorell, X., Navarro, N., Torres, J., and Ayguadé, E., Energy accounting for shared virtualized environments under DVFS using PMC-based power models, Future Generation Computer Systems, vol. 28, no. 2. pp. 457 - 468, 2011.
C. Villavieja, Etsion, Y., Ramirez, A., and Navarro, N., FELI: HW/SW support for On-Chip Distributed Shared Memory in Multicores, Euro-Par. 2011.
M. Shafiq, Pericàs, M., Navarro, N., and Ayguadé, E., TARCAD: A template architecture for reconfigurable accelerator designs, IEEE Symposium on Application Specific Processors (SASP). pp. 8-15, 2011.
2009
J. Cabezas, Araya-Polo, M., Gelado, I., Navarro, N., and Cela, J. M., High-Performance Reverse Time Migration on GPU, XXVIII International Conference of the Chilean Computer Society - XIII Workshop on Parallel and Distributed Systems (WSDP). 2009.
V. J. Jiménez, Vilanova, L., Gelado, I., Gil, M., Fursin, G., and Navarro, N., Predictive Runtime Code Scheduling for Heterogeneous Architectures. Proc. of the 4th International Conference on High Performance Embedded Architectures and Compilers - HiPEAC '09, 2009.