Method, mechanism and computer program product for executing several tasks in a multithreaded processor and for providing estimates for worst-case execution times

 Status:
GRANTED
 Publication number:
EP2192492
 Priority date:
 Inventor:
Francisco Javier Cazorla Almeida
 Applicant:
Barcelona Supercomputing Center - Centro Nacional De Supercomputacion (BSC-CNS)

Abstract

The invention relates a method for executing several tasks in a multithreaded (MT) processor, each task having, for every hardware shared resource from a predetermined set of hardware shared resources in the MT processor, one associated artificial time delay that is introduced when said task accesses said hardware shared resource, the method comprising step (a) of establishing, for every hardware shared resource and each task to be artificially delayed, the artificial delay to be applied to each access of said task to said hardware shared resource; step (b) of performing the following steps (b1) to (b4) on the access of each task to be artificially delayed to every hardware shared resource in the predetermined set of hardware shared resources in the MT processor: step (b1) of verifying if a request is ready to be sent to said hardware shared resource; in case of positive result, Step (b2) of verifying if the hardware shared resource is ready to accept said request; in case of positive result, step (b3) of delaying said request by the artificial delay established for said hardware shared resource; step (b4) of allowing the request of the task to access said hardware shared resource. The method is used for computing worst case execution times of hard real-time tasks.

Patent family

  • US8555284 (B2)
  • ES2399683 (T3)