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2013

TM-dietlibc: A TM-aware Real-world System Library

The 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013)

V. Smiljkovic, M. Nowack, N. Miletić, T. Harris, O. Unsal, A. Cristal, and M. Valero
Circuit Design of a Novel Adaptable and Reliable L1 Data Cache

23rd ACM international conference on Great lakes symposium on VLSI

A. Seyedi, G. Yalcin, O. Unsal, and A. Cristal
Fault Tolerance for Multi-Threaded Applications by Leveraging Hardware Transactional Memory

10th conference on ACM Computing Frontiers

G. Yalcin, O. Unsal, and A. Cristal
On the Selection of Adder Unit in Energy Efficient Vector Processing

14th International Symposium on Quality Electronic Design (ISQED)

Ivan Ratkovic, O. Palomar, Milan Stanic, O. Unsal, A. Cristal, and M. Valero
FaulTM: Error Detection and Recovery Using Hardware Transactional Memory

ACM/IEEE Design, Automation, and Test in Europe (DATE)

G. Yalcin, O. Unsal, and A. Cristal
Task Sampling: Computer Architecture Simulation in the Many-Core Era

22nd international conference on Parallel Architectures and Compilation Techniques

T. Grass
Supercomputing with commodity CPUs: are mobile SoCs ready for HPC?

SC13: International Conference for High Performance Computing, Networking, Storage and Analysis

N. Rajovic, P. Carpenter, I. Gelado, N. Puzovic, A. Ramirez, and M. Valero
Data placement in HPC architectures with heterogeneous off-chip memory

31nd IEEE International Conference on Computer Design

M. Pavlovic, N. Puzovic, and A. Ramirez
Parallelizing general histogram application for CUDA architectures

2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIII)

U. Milic, I. Gelado, N. Puzovic, A. Ramirez, and M. Tomasevic
Trace Filtering of Multithreaded Applications for CMP Memory Simulation

IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2013)

A. Rico, A. Ramirez, and M. Valero

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