Publications

Export results as:

Showing 91 - 100 results of 101

2011

RVC-based time-predictable faulty caches for safety-critical systems.

IOLTS

J. Abella, E. Quinones, F. Cazorla, M. Valero, and Y. Sazeides
IA3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems

M. Paolieri, E. Quinones, F. Cazorla, R. I. Davis, and M. Valero
A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-Threaded Hard Real-Time Tasks

M. Paolieri, E. Quinones, J. Wolf, Z. Petrov, F. Cazorla, S. Uhrig, and T. Ungerer
RVC: A Mechanism for Time-Analyzable Real-Time Processors with Faulty Caches

J. Abella, E. Quinones, F. Cazorla, Y. Sazeides, and M. Valero

2010

Hard Real-Time Capable Multicore Processors for Space Applications

M. Moreto, M. Paolieri, J. Abella, E. Quinones, F. Cazorla, and M. Valero
Use of Randomized Caches in Hard Real-Time Systems

6th ACACES 2010 (Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems)

L. Kosmidis, E. Quinones, J. Abella, F. Cazorla, G. Bernat, and E. D. Berger
MERASA: Multi-Core Execution of Hard Real-Time Applications Supporting Analysability

T. Ungerer, F. Cazorla, P. Sainrat, G. Bernat, Z. Petrov, H. Casse, C. Rochange, E. Quinones, S. Uhrig, M. Gerdes, I. Guliashvili, M. Houston, F. Kluge, and S. Met

2009

An Analyzable Memory Controller for Hard Real-Time CMPs

IEEE Embedded Systems Letters

M. Paolieri, E. Quinones, F. Cazorla, and M. Valero
Using Randomized Caches in Probabilistic Real-Time Systems

E. Quinones, E. D. Berger, G. Bernat, and F. Cazorla
Hardware Support for WCET Analysis of Multicore Systems

M. Paolieri, E. Quinones, F. Cazorla, G. Bernat, and M. Valero

Pages