Publications

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2004

Analysis of a high performance DRAM/SRAM memory scheme for fast packet buffers

M. March, J. García, L.. Cerdá, and M. Valero
A Hybrid DRAM/SRAM Design for Fast Packet Buffers

J. García, M. March, L.. Cerdá, J. Corbal, and M. Valero
Heterogeneity-Aware Architectures

XV Jornadas de Paralelismo

C. Acosta, A. Falcón, A. Ramirez, and M. Valero
A Low-Complexity Fetch Architecture for High-Performance Superscalar Processors

ACM Transactions on Architecture and Code Optimization

O. J. Santana, A. Ramirez, J. Lluis Larriba-Pey, and M. Valero
Predictable Performance in SMT Processors

Computing Frontiers (CF'04)

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero
Limits on Early Release of Physical Registers

J. J. Alastruey, T. Monreal, V. Viñals, and M. Valero
Aggressive Speculative Execution for Hidding Memory Latency

A. Pajuelo, A. González, and M. Valero
Scalability and Complexity of 2-Dimensional SIMD Extensions

XV Jornadas de Paralelismo

M. Álvarez, F. Sánchez, E. Salami, A. Ramirez, and M. Valero
Analysis of Traffic Traces for Statefull Applications

J. Verdú, J. García, M. Nemirovsky, and M. Valero
Selecting Where to Simulate SPEC2000 Using Streams Analysis

XV Jornadas de Paralelismo

A. Falcón, O. J. Santana, A. Ramirez, and M. Valero

Pages