Publications

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Showing 11 - 20 results of 27

2011

TARCAD: A template architecture for reconfigurable accelerator designs

IEEE Symposium on Application Specific Processors (SASP)

M. Shafiq, M. Pericas, N. Navarro, and E. Ayguade
Assessing Accelerator-based HPC Reverse Time Migration

Transactions on Parallel and Distributed Systems, Special Issue on Accelerators

M. Araya-Polo, J. Cabezas, M. Hanzich, M. Pericas, E. Morancho, I. Gelado, M. Shafiq, F. Rubio, J M.. Cela, E. Ayguade, N. Navarro, and M. Valero

2008

Affordable kilo-instruction processors

M. Pericas
A Two-Level Load/Store Queue Based on Execution Locality

The 35th International Symposium on Computer Architecture (ISCA 2008)

M. Pericas, A. Cristal, F. Cazorla, R. González, A. Veidenbaum, D. A. Jiménez, and M. Valero

2007

A Flexible Heterogeneous Multi-Core Architecture

The 2007 International Conference on Parallel Architectures and Compilation Techniques (PACT 2007)

M. Pericas, A. Cristal, F. Cazorla, R. González, D. Jiménez, and M. Valero

2006

Boosting ILP{&}TLP with the Flexible Multi-Core (FMC)

2006 Advanced Computer Architecture and Compilation for Embedded Systems (ACACES-06)

M. Pericas, A. Cristal, R. González, F. Cazorla, D. A. Jiménez, and M. Valero
A decoupled KILO-instruction processor

The 12th International Symposium on High-Performance Computer Architecture (HPCA-12)

M. Pericas, A. Cristal, R. González, D. Jiménez, and M. Valero

2005

Arquitectura Simétrica Clusterizada basada en el Contenido

XVI Jornadas de Paralelismo

R. González, A. Cristal, M. Pericas, A. Veidenbaum, and M. Valero
Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor

6th International Symposium on High Performance Computing (ISHPC-VI 2005)

M. Pericas, A. Cristal, R. González, D. A. Jiménez, and M. Valero
Decoupled State-Execute Architecture

6th International Symposium on High Performance Computing (ISHPC-VI 2005)

M. Pericas, A. Cristal, R. González, and M. Valero

Pages