Publications

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2006

A Simple Speculative Load Control Mechanism for Energy Saving

T. Ramírez, M. Pajuelo, O. J. Santana, and M. Valero
Performance Analysis of Sequence Alignment Applications

IISWC, IEEE Internacional Symposium on Workload Characterization

F. Sánchez, E. Salami, A. Ramirez, and M. Valero
Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors

T. Morad, U. Weiser, A. Kolodny, M. Valero, and E. Ayguade
A DRAM/SRAM Memory Scheme for Fast Packet Buffers

J. Vidal, M. March, L.. Cerdá, J. Corbal, and M. Valero
Predictable Performance in SMT processors: Synergy Between the OS and SMTs

IEEE Transactions on Computers

F. Cazorla, P. Knijnenburg, R. Sakellariou, E. Fernández, A. Ramirez, and M. Valero

2005

A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation

IEEE International Conference on Computer Design (ICCD-2005)

M. A. Ramírez, A. Cristal, M. Valero, A. Veidenbaum, and L. A. Villa
Arquitectura Simétrica Clusterizada basada en el Contenido

XVI Jornadas de Paralelismo

R. González, A. Cristal, M. Pericas, A. Veidenbaum, and M. Valero
Towards the Loop Processor Architecture

XVI Jornadas de Paralelismo

A. García, P. Medina, E. Fernández, O. J. Santana, A. Cristal, and M. Valero
KIMP: Multicheckpointing Multiprocessors

XVI Jornadas de Paralelismo

E. Vallejo, M. Galluzzi, A. Cristal, F. Vallejo, R. Beivide, P. Stenström, J. E. Smith, and M. Valero
Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor

6th International Symposium on High Performance Computing (ISHPC-VI 2005)

M. Pericas, A. Cristal, R. González, D. A. Jiménez, and M. Valero

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