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2011

Simulating Whole Supercomputer Applications

IEEE Micro

J. González, J. Giménez, M. Casas, M. Moreto, A. Ramirez, J. Labarta, and M. Valero
RVC-based time-predictable faulty caches for safety-critical systems.

IOLTS

J. Abella, E. Quinones, F. Cazorla, M. Valero, and Y. Sazeides
A Case for Energy-Aware Accounting and Billing in Large-Scale Computing Facilities Cost Metrics and Design Implications.

IEEE Micro

V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, P. Bose, and M. Valero
Characterizing Power and Temperature Behavior of POWER6-Based System

IEEE Journal of Emerging and Selected Topics in Circuits and Systems

V. Jimenez, F. Cazorla, R. Gioiosa, M. Valero, C. Boneti, E. Kursun, C. Cher, C. Isci, A. Buyuktosunoglu, and P. Bose
STM2: A Parallel STM for High Performance Simultaneous Multi-Threading Systems

The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT)

G. Kestor, R. Gioiosa, T. Harris, A. Cristal, O. Unsal, M. Valero, and I. Hur
Trace-driven simulation of multithreaded applications

2011 IEEE International Symposium on Performance Analysis of Systems and Software

A. Rico, A. Duran, F. Cabarcas, Y. Etsion, A. Ramirez, and M. Valero
Parameterizing Multicore Architectures for Multiple Sequence Alignment

2011 International Conference on Computing Frontiers

S. Isaza, F. Sánchez, G. N. Gaydadjiev, A. Ramirez, and M. Valero
Scalable multicore architectures for long DNA sequence comparison

Concurrency and Computation Practice and Experience

F. Sánchez, F. Cabarcas, A. Ramirez, and M. Valero
Simulation environment to study overlapping of communication and computation

V. Subotic, J. Labarta, and M. Valero
A simulation framework to automatically analyze the communication-computation overlap in scientific applications

V. Subotic, J C. Sancho, J. Labarta, and M. Valero

Pages