HiPEAC2: High Performance and embedded Architecture and Compilation

Status: Finished Start:

01/02/2008

End:

31/01/2012

Software

Simulation

Platforms

Performance

Mobility

Roadmap

Industry

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Main Investigators

EDUARD AYGUADE PARRA

COMPUTER SCIENCES DEPARTMENT ASSOCIATE DIRECTOR

Computer Sciences

eduard [dot] ayguade [at] bsc [dot] es

+34 934134037

View Research Lines

Improving Virtual Memory

Memory systems for HPC

Microserver architectures and system software

Mobile and embedded-based HPC

Neural networks for data-streams

Preemptive multiprogramming on GPUs

Runtime aware architectures

Investigators