LOCA SERIES. Reading Club. 4th session

Date: 16/May/2023 Time: 16:00


BSC Builidng, 1st floor, Room 1-3-12 and Zoom

Primary tabs


The general objective of LOCA Technical sessions is to value the knowledge, talent and experience of the center's workers and researchers, and support the creation of a multidisciplinary work team based on the strengths of each and every one of its members.
To contribute to a sustainable and organic growth of the hardware design area at BSC, we propose organizing Internal LOCA Tech sessions. A monthly event whose objectives are: 1) promotion of internal BSC talent (Tech-Talk sessions), and 2) continuous learning/development mechanism (Reading club sessions).
Tech-Talk session: Technical presentations on specific topics with the aim of putting the spotlight on the most senior and post-doc community’s background and know-how, and also making visible the research and/or interests areas of work of each of those members.
Reading club session: Technical sessions in the form of a presentation with the objectives of: 1) actively involving members with less experience in research activities, and 2) offering a “light-weight” training/retraining mechanism for all members that allows them to keep up to date with the state of the art.

Rehearsal for ISC conferences and RISC-V Summit

Topic: Optimizations for very long and sparse vector operations on a RISC-V VPU: a work-in progress (20 min)

Abstract: A significant scope to vectorize the present-day workloads in scientific computations and machine learning have highlighted Vector Processing Unit (VPU) as a target accelerator. There is a need to efficiently handle these vector operations involving very long vectors and sparse vectors to improve performance as well as to save energy. This talk presents enhancements to a RISC-V VPU to achieve this and a supporting infrastructure around the VPU in a many-core system. The talk also discusses the current results on the enhanced VPU with pointers to the planned modifications.

Short bio: Gopinath Mahale Gopinath V. Mahale received his Bachelors in Electronics and communication engineering from the Visvesvaraya Technological University, India, in 2007, his Masters in electronics from the University of Pune, India, in 2011, and Ph.D. degree in electronic systems engineering from the Indian Institute of Science (IISc), Bangalore, India, in 2017. Currently he is a researcher at Barcelona Supercomputing Center (BSC). Prior to this he has worked as a Project Engineer at

Wipro Technologies, as a Research Associate at the IISc, as a Postdoctoral Research Associate at the University of Paderborn, Germany and as a Staff Engineer at the Samsung Advanced Institute of Technology, SRIB, Bengaluru, India. His research interests include domain-specific hardware acceleration, machine learning, low power computations for deep learning, algorithm-architecture co-design and high-performance computing.

Topic: Challenges and opportunities for RISC-V Architectures towards Genomics-based workloads (20min)

Abstract: The use of large-scale supercomputing architectures is a hard requirement for scientific computing Big-Data applications. An example is genomics analytics, where millions of data transformations and tests per patient need to be done to find relevant clinical indicators. Therefore, to ensure open and broad access to high-performance technologies, governments, and academia are pushing toward the introduction of novel computing architectures in large-scale scientific environments. This is the case of RISC-V, an open-source and royalty-free instruction-set architecture.

To evaluate such technologies, here we present the Variant-Interaction Analytics use case benchmarking suite and datasets. Through this use case, we search for possible genetic interactions using computational and statistical methods, providing a representative case for heavy ETL (Extract, Transform, Load) data processing. Current implementations are implemented in x86-based supercomputers (e.g. MareNostrum-IV at the Barcelona Supercomputing Center (BSC)), and future steps propose RISC-V as part of the next MareNostrum generations.

Here we describe the Variant Interaction Use Case, highlighting the characteristics leveraging high-performance computing, indicating the caveats and challenges towards the next RISC-V developments and designs to come from a first comparison between x86 and RISC-V architectures on real Variant Interaction executions over real hardware implementations.

Short bios: Gonzalo Gómez received his BSc degree in Telecomunications Engineering from Universitat Politècnica de Catalunya (UPC), Barcelona in 2016. He completed his MSc degree in Artificial Intelligence from Universitat de Barcelona (UB), Universidat Rovira I Virgill (URV) and UPC, Catalunya in 2018. Since 2018, he has been a PhD student at the department of Computer Science in Barcelona Supercomputing Center (BSC) and Universitat Politécnica de Catalunya (UPC), Spain.

Aaron Call received the B.S. and Ph.D. degrees from the BarcelonaTech-Universitat Politècnica de Catalunya (UPC), in 2014 and 2022, respectively. He is currently a Postdoctoral Researcher within the Data-Centric Computing, Barcelona Supercomputing Center. On winter 2019 he was a research intern at Intel Labs on Portland, Oregon. His research evolves around resource disaggregation and management on the cloud-edge context. Currently he is conducting research on disaggregation for heterogeneous resources and novel architectures in the cloud-edge continuum.

Topic: MEDEA: Improved Memory-level parallelism in a Decoupled Execute/Access vector accelerator (15min)

Abstract: The performance of Machine learning and graph-based applications is hampered by the inefficient use of memory bandwidth caused by their sparse access patterns. In order to improve bandwidth utilization in a RISC-V based vector accelerator, the Memory Engine for Decoupled Execute/Access (MEDEA) combines a hardware engine that handles vector loads and stores efficiently with a dedicated core that supports memory-intense operations such as spinlocks and memcpy. Although work on MEDEA is still in progress, simulations show that it can have a large impact on the performance of sparse-memory applications such as SpMV.

Short bio: Umair Riaz received his BSc in Electronic Engineering from the University of Engineering and Technology (UET), Taxila, Pakistan, in 2018. Since 2018, he has been working in the industry before joining Barcelona Supercomputing Center (BSC) in 2022, where he is working as an RTL Engineer. His expertise lies around digital systems designing in general and RISC-V processors in particular.


Presenters: Gopinath Vasanth Mahale, European Exascale Accelerator Established Researcher, CS, BSC, Gonzalo Gómez, Data Centric Computing Visitor, CS, BSC, Aaron Call, Data Centric Computing Recognised Researcher, CS, BSC, Umair Riaz, European Exascale Accelerator Junior Research Engineer, CS, BSC
Chair: Elias Augusto Perdomo Hourne, European Exascale Accelerator First Stage Researcher, CS, BSC