LOCA SERIES. Reading Club. 3rd session

Date: 18/Apr/2023 Time: 16:00


BSC Builidng, 1st floor, Room 1-3-12 and online via zoom

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The general objective of LOCA Technical sessions is to value the knowledge, talent and experience of the center's workers and researchers, and support the creation of a multidisciplinary work team based on the strengths of each and every one of its members.
To contribute to a sustainable and organic growth of the hardware design area at BSC, we propose organizing Internal LOCA Tech sessions. A monthly event whose objectives are: 1) promotion of internal BSC talent (Tech-Talk sessions), and 2) continuous learning/development mechanism (Reading club sessions).
Tech-Talk session: Technical presentations on specific topics with the aim of putting the spotlight on the most senior and post-doc community’s background and know-how, and also making visible the research and/or interests areas of work of each of those members.
Reading club session: Technical sessions in the form of a presentation with the objectives of: 1) actively involving members with less experience in research activities, and 2) offering a “light-weight” training/retraining mechanism for all members that allows them to keep up to date with the state of the art.

Topic and Presenter: HLIB & OoO core composer, Jonnatan Mendoza, Computer Architecture for Parallel Paradigms Senior Research Engineer, CS

Abstract: System Verilog is a powerful hardware description language; however, designing complex hardware IPs commonly requires the integration of well-known standard structures. This work proposes a collaborative work methodology and code conventions to build a general-purpose, open-source System Verilog hardware library. HLIB aims to contribute with commonly used, highly parametrized modules looking to reduce micro-architectural hardware implementation overhead while enhancing code maintenance, modularity, readability, and reliability, but also helping to reduce verification efforts of highly complex hardware IPs utilizing this library. HLIB looks to reduce the development time implied in RTL design by expressing a conscience and complete engineering cycle, code guidelines, conventions, and miscellaneous tools for hardware development, together with a set of hardware modules that already follow this proposal to invite hardware developers to be benefited of the constant contributions of this work. As a result of the continuous development of HLIB modules, the concept of a core composer is in the project roadmap's following objective, consolidating a flexible OoO-Core generator targeting a wide range of PPA tradeoffs.

Short Bio: Jonnatan Mendoza is a Computer Science Researcher with four years of experience in hardware design and six years in electronics engineering. He is a doctorate student at the Polytechnic University of Catalunya and a research engineer at Barcelona Supercomputing Center. He has worked on Lagarto, DRAC, and EPI projects as an RTL designer, and his expertise includes computer architecture design for scalar multithreaded and vector architectures. He is a RISCV enthusiast focused on HPC.

Chair: Xabier Abancens, European Exascale Accelerator Research Engineer, Computer Sciences


Presenters: Jonnatan Mendoza, Computer Architecture for Parallel Paradigms Senior Research Engineer, CS, BSC
Chairs: Xabier Abancens, European Exascale Accelerator Research Engineer, CS, BSC