Miquel Moreto

2008

• Dynamic Cache Partitioning Based on the MLP on Cache Misses.

  Transactions on HiPEAC

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• Multicore Resource Management

  IEEE Micro

  K. J. Nesbit, M. Moreto, F. Cazorla, A. Ramirez, M. Valero, and J. E. Smith
• Architecture performance prediction using evolutionary artificial neural networks

  P. A. Castillo, A. M. Mora, J J. Merelo, J L. Laredo, M. Moreto, F. Cazorla, M. Valero, and S. A. McKee
• MLP-aware dynamic cache partitioning

  2008 International Conference on High Performance Embedded Architectures & Compilers (HiPEAC 2008)

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• Evolutionary system for prediction and optimization of hardware architecture performance

  P. A. Castillo, J J. Merelo, M. Moreto, F. Cazorla, M. Valero, A. M. Mora, J L. Laredo, and S. A. McKee
• Virtual Private Machines: Hardware/Software Interactions in the Multicore Era

  K. J. Nesbit, M. Moreto, F. Cazorla, A. Ramirez, M. Valero, and J. E. Smith

2007

• Online Prediction of Throughput for Different Cache Sizes

  XVIII Jornadas de Paralelismo

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• MLP-aware dynamic cache partitioning

  International Conference on Parallel Architectures and Compilation Techniques (PACT)

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• Explaining Dynamic Cache Partitioning Speed Ups

  IEEE Computer Architecture Letters

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero
• Online Prediction of Applications Cache Utility

  International Symposium on Systems, Architectures, MOdeling and Simulation (SAMOS)

  M. Moreto, F. Cazorla, A. Ramirez, and M. Valero