Verification engineer for vector accelerators (RE2 - RE3)

Job Reference



Verification engineer for vector accelerators (RE2 - RE3)

Closing Date

Thursday, 30 June, 2022
Reference: 114_22_CS_V_RE2-3
Job title: Verification engineer for vector accelerators (RE2 - RE3)


About BSC
The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, and is a hosting member of the PRACE European distributed supercomputing infrastructure. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 770 staff from 55 countries.

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Context And Mission
BSC is looking for talented and motivated professionals with expertise in Processor Design, Validation and IP integration for a HPC RISC-V HPC accelerator in the new EuPilot project (

The European PILOT will deliver the first All-European open source and open standard based software and hardware integrated HPC system by creating an autonomous set of accelerators designed, implemented, manufactured, and deployed in Europe. The accelerators will be manufactured in the new European Global Foundries 12nm advanced silicon technology, a major demonstration of European technology independence.

BSC contributes a RISC-V vector accelerator to EuPilot and verifying its functional correctness is key for success.
Key Duties
  • You will use your design and verification expertise to verify complex digital designs, focused on vector units and other accelerators.
  • You will collaborate closely with design and verification engineers in active projects and perform hands-on verification, and contribute to design, build, and integrate the designs.
  • Using your UVM, SystemVerilog and problem-solving skills, you will build efficient and effective verification environments that exercise processor designs through their corner-cases and expose all types of bugs.
  • You will be responsible for the full life cycle of verification, including verification planning, test and assertion implementation, failure triaging, debugging, coverage definition and others.
  • You will automatize the processes by creating and maintaining verification & post-processing scripts for verification, triaging, coverage and debugging.
  • You will train others in the configuration, deployment, use and/or maintenance of verification software, scripts and workflows.
  • Education
    • MS degree in Electrical Engineering, Computer Engineering, or equivalent
    • Engineering degree (Ph.D. preferred) with demonstrable professional experience.
  • Essential Knowledge and Professional Experience
    • Experienced with the full verification life cycle from test planning to sign-off.
    • Working knowledge of Universal Verification Methodology(UVM), writing test plans, simulating, debugging, and documenting results
    • Knowledge of and experience with industry-standard simulators (Model/QuestaSim, VCS, etc.), revision control systems and regression systems.
    • Experienced in key DV methodologies: UVM, SystemVerilog Assertions, functional coverage, Assembly/C-based random/constrained-random Verification, Formal Verification, Verification IPs.
    • Experienced in developing a DV plan based on Functional Specification, create and build the necessary verification test bench/infrastructure, develop tests and verify the design.
    • Creation of validation plans of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
    • Ability identify functional coverage working with cross functional teams (DV/Arch/Design). Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage measures to identify verification holes and to show progress towards tape-out.
    • Implementation of SystemVerilog UVM testbenches for a complex digital design, coupling with a reference model for co-simulation.
    • Strong debugging skills and able to work with design engineers to deliver functionally correct design blocks. Execute tests. Analyze data, prepare reports summarizing results and statistics.
    • Strong scripting experience using scripting languages like Python, Perl, Bash or Tcl to perform support adjustments and customization of design and verification flows. Familiarity with Linux.
    • Excellent interpersonal, written, and verbal communication skills.
    • Ability to work as part of a cross-functional team according to an established timeline
    • Fluency in English is essential, Spanish is welcome.
  • Additional Knowledge and Professional Experience
    • Deep understanding of Modern in-order and out-of-order processor core and accelerator designs.
    • Experience with one or more Instruction Set Architectures (ISAs) including RISC-V, and their implementation within in-order and out-of-order processor cores.
    • Experience with verification of top-level and processor-based SoC and DLP acceleration (GPU/SIMD/Vector) is a big plus.
  • Competences
    • The candidate must be an effective communicator, multitask, and work well on collaborative designs.
    • Keeps abreast of technology trends.
    • Ability to think creatively.
    • Ability to work independently and make decisions.
    • Ability to take initiative, prioritize and work under set deadlines and pressure.
  • The position will be located at BSC within the Computer Sciences Department
  • We offer a full-time contract, a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, tickets restaurant, private health insurance, fully support to the relocation procedures
  • Duration: Temporary - 18 months renewable
  • Salary: we offer a competitive salary commensurate with the qualifications and experience of the candidate and according to the cost of living in Barcelona
  • Starting date: May 2022
Applications procedure and process
All applications must be made through BSC website and contain:
  • A full CV in English including contact details
  • A Cover Letter with a statement of interest in English, including two contacts for further references - Applications without this document will not be considered

    In accordance with the OTM-R principles, a gender-balanced recruitment panel is formed for every vacancy at the beginning of the process. After reviewing the content of the applications, the panel will start the interviews, with at least one technical and one administrative interview. A profile questionnaire as well as a technical exercise may be required during the process.

    The panel will make a final decision and all candidates who had contacts with them will receive a feedback with details on the acceptance or rejection of their profile.

    At BSC we are seeking continuous improvement in our recruitment processes, for any suggestions or feedback/complaints about our Recruitment Processes, please contact recruitment [at] bsc [dot] es.

    For more information follow this link
The vacancy will remain open until suitable candidate has been hired. Applications will be regularly reviewed and potential candidates will be contacted.
OTM-R principles for selection processes
BSC-CNS is committed to the principles of the Code of Conduct for the Recruitment of Researchers of the European Commission and the Open, Transparent and Merit-based Recruitment principles (OTM-R). This is applied for any potential candidate in all our processes, for example by creating gender-balanced recruitment planels and recognizing career breaks etc.
BSC-CNS is an equal opportunity employer committed to diversity and inclusion. We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.
For more information follow this link


Application Form

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