RTL engineer for an out-of-order processor

Job Reference



RTL engineer for an out-of-order processor

Closing Date

Sunday, 16 October, 2022
Reference: 100_22_CS_CAPP_RE
Job title: RTL engineer for an out-of-order processor


About BSC
The Barcelona Supercomputing Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, and is a hosting member of the PRACE European distributed supercomputing infrastructure. The mission of BSC is to research, develop and manage information technologies in order to facilitate scientific progress. BSC combines HPC service provision and R&D into both computer and computational science (life, earth and engineering sciences) under one roof, and currently has over 770 staff from 55 countries.

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Context And Mission
BSC is constructing a full RISCV ecosystem, from the design of the processors to the tape-out of them; also, BSC is working in the full software stack.
In this context, BSC has to develop an HPC out-of-order vector RISCV processor. This vacancy is for several engineers for this processor, from junior applicants to more senior profiles.
Key Duties
  • You will use your design expertise to design and build complex digital designs focused on OoO processors, vector units and uncore
  • You will collaborate closely with design architects and verification engineers and perform hands-on design, writing RTL code.
  • Design integration, logic synthesis and design optimization for area, timing and power.
  • Participating in chip bring-up and testing.
  • Education
    • Computer / Electrical Engineering degree or equivalent level of professional experience.
  • Essential Knowledge and Professional Experience
    • Knowledge of RTL Design, logic synthesis and timing closure.
    • Proficiency in Verilog/VHDL/SystemVerilog is required.
    • Modern out-of-order processor core and accelerator designs, with experience in one or more of the following areas: fetch, decode, branch prediction, renaming and scheduling, out-of-order execution, re-order buffer, integer, and floating-point execution, vector execution, load/store execution, caches, and memory subsystem.
    • Agile development and open source development, deployment, and support, including GitHub or equivalent.
  • Additional Knowledge and Professional Experience
    • Strong scripting/programming in C/C++, Tcl, Python, Perl/Csh is a plus.
    • Familiarity with Mentor, Synopsys, Cadence, Xilinx, and other EDA tools.
    • Strong analytics skills, experience with DSPs, MCUs, FPGAs, SoC, and low-power design will be considered a plus.
    • DLP (GPU/SIMD/Vector) hardware development expertise is a big plus.
  • Competences
    • Fluency in English is essential, Spanish and Catalan is welcome.
    • Effective communication, multitasking, and working well on collaborative designs
    • Keeping abreast on technology trends.
    • Ability to think creatively.
    • Ability to work independently and make decisions.
    • Ability to take initiative, prioritize and work under set deadlines and pressure.
  • The position will be located at BSC within the Computer Sciences Department
  • We offer a full-time contract, a good working environment, a highly stimulating environment with state-of-the-art infrastructure, flexible working hours, extensive training plan, tickets restaurant, private health insurance, fully support to the relocation procedures
  • Duration: Open-ended contract due to technical and scientific activities linked to the project and budget duration
  • Salary: we offer a competitive salary commensurate with the qualifications and experience of the candidate and according to the cost of living in Barcelona
  • Starting date: 1/4/2022
Applications procedure and process
All applications must be made through BSC website and contain:
  • A full CV in English including contact details
  • A Cover Letter with a statement of interest in English, including two contacts for further references - Applications without this document will not be considered

    In accordance with the OTM-R principles, a gender-balanced recruitment panel is formed for every vacancy at the beginning of the process. After reviewing the content of the applications, the panel will start the interviews, with at least one technical and one administrative interview. A profile questionnaire as well as a technical exercise may be required during the process.

    The panel will make a final decision and all candidates who had contacts with them will receive a feedback with details on the acceptance or rejection of their profile.

    At BSC we are seeking continuous improvement in our recruitment processes, for any suggestions or feedback/complaints about our Recruitment Processes, please contact recruitment [at] bsc [dot] es.

    For more information follow this link
The vacancy will remain open until suitable candidate has been hired. Applications will be regularly reviewed and potential candidates will be contacted.
OTM-R principles for selection processes
BSC-CNS is committed to the principles of the Code of Conduct for the Recruitment of Researchers of the European Commission and the Open, Transparent and Merit-based Recruitment principles (OTM-R). This is applied for any potential candidate in all our processes, for example by creating gender-balanced recruitment planels and recognizing career breaks etc.
BSC-CNS is an equal opportunity employer committed to diversity and inclusion. We are pleased to consider all qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or any other basis protected by applicable state or local law.
For more information follow this link


Application Form

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Please, upload your CV document using the following name structure: Name_Surname_CoverLetter
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Please, upload your CV document using the following name structure: Name_Surname_OtherDocument
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** Consider that the information provided in relation to gender and nationality will be used solely for statistical purposes.