Publications

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Q. Liu, Moreto, M., Abella, J., Cazorla, F. J., and Valero, M., SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems, 2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)2017 29th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Campinas, Brazil, pp. 73 - 80, 2017.
S. Zhuang and Casas, M., Iteration-Fusing Conjugate Gradient, Proceedings of the 31st ACM International Conference on Supercomputing (ICS). 2017.
C. Ortega, Moreto, M., Casas, M., Bertran, R., Buyuktosunoglu, A., Eichenberger, A. E., and Bose, P., libPRISM: An Intelligent Adaption of Prefetch and SMT Levels, Proceedings of the 31st ACM International Conference on Supercomputing (ICS). 2017.
Q. Liu, Moreto, M., Abella, J., Cazorla, F., Jiménez, D. A., and Valero, M., Sensible Energy Accounting with Abstract Metering for Multicore Systems, ACM Transactions on Architecture and Code Optimization (TACO), vol. 12, no. 11th International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC). 2016.
Q. Liu, Moreto, M., Abella, J., Cazorla, F., and Valero, M., DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems, ACM Transactions on Design Automation of Electronic Systems, vol. 22. pp. 1 - 26, 2016.
C. Camarero, Vallejo, E., and Beivide, R., Topological Characterization of Hamming and Dragonfly Networks and Its Implications on Routing, 11th High Performance and Embedded Architecture and Compilation (HiPEAC-2015). ACM, Amsterdam, The Netherlands, 2015.
D. Prat, Ortega, C., Casas, M., Moreto, M., and Valero, M., Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7, 6th International Workshop on Adaptive Self-tuning Computing Systems. arXiv.org, Amsterdam, Netherlands, pp. 1–6, 2015.
V. J. Jiménez, Buyuktosunoglu, A., Bose, P., O’Connell, F., Cazorla, F., and Valero, M., Increasing Multicore System Efficiency through Intelligent Bandwidth Shifting, International Symposium on High- Performance Computer Architecture (HPCA). pp. 39-50, 2015.
M. Amaral, Polo, J., Carrera, D., Mohomed, I., and Unuvar, M., Performance Evaluation of Microservices Architectures using Containers, 14th IEEE International Symposium on Network Computing and Applications (IEEE NCA15). pp. 27-34, 2015.
P. Fuentes, Vallejo, E., Garcia, M., Rodríguez, G., Minkenberg, C., and Valero, M., Contention-based Nonminimal Adaptive Routing in High-radix Networks, 29th IEEE International Parallel & Distributed Processing Symposium. pp. 103-112, 2015.
I. Perez, Vallejo, E., and Bosque, J. Luis, TraceRep: Gateway for Sharing and Collecting Traces in HPC Systems, Science Gateways (IWSG), 2015 7th International Workshop on . pp. 67-72, 2015.
G. Ozen, Ayguade, E., and Labarta, J., On the Roles of the Programmer, the Compiler and the Runtime System When Programming Accelerators in OpenMP, Using and Improving OpenMP for Devices, Tasks, and More. IWOMP 2014. Lecture Notes in Computer Science, vol. 8766. Springer International Publishing, pp. 215-229, 2014.
C. Camarero, Vallejo, E., and Beivide, R., Topological Characterization of Hamming and Dragonfly Networks and Its Implications on Routing, ACM Transactions on Architecture and Code Optimization, vol. 11. ACM, New York, NY, USA, pp. 1–25, 2014.
C. Camarero, Martinez, C., and Beivide, R., Lattice Graphs for High-Scale Interconnection Topologies, IEEE Transactions on Parallel and Distributed Systems. IEEE, pp. 2506-2519, 2014.
Q. Liu, Moreto, M., Abella, J., Cazorla, F., and Valero, M., DReAM: Per-Task DRAM Energy Metering in Multicore Systems, 20th International EUROPAR Conference. European Conference on Parallel and Distributed Computing. Springer, Porto, Portugal, pp. 111–123, 2014.
P. Fuentes, Bosque, J. L., Beivide, R., Valero, M., and Minkenberg, C., Characterizing the Communication Demands of the Graph500 Benchmark on a Commodity Cluster, International Symposium on Big Data Computing (BDC 2014). IEEE/ACM, London, UK, 2014.
V. Jiménez, Gioiosa, R., Cazorla, F., Buyuktosunoglu, A., Bose, P., and O'Connell, F. P., Making Data Prefetch Smarter: Adaptive Prefetching on POWER7, 21st International Conference on Parallel Architectures and Compilation Techniques (PACT-2012). ACM, Minneapolis, United States, pp. 137–146, 2012.
C. Luque, Moreto, M., Cazorla, F., Gioiosa, R., Buyuktosunoglu, A., and Valero, M., CPU Accounting for Multicore Processors, IEEE Transactions on Computers, vol. 61. pp. 251–264, 2012.

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