SORS: How to Completely Destroy Good Accelerator Design with Bad I/O Design in SoC-FPGA

Fecha: 13/Sep/2019 Time: 10:30

Place:

Sala d'actes de la FiB, Campus Nord

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Objectives

Abstract: Unlike traditional PCIe-based FPGA accelerators, heterogeneous SoC-FPGA devices provide tighter integrations between software running on CPUs and hardware accelerators. Modern heterogeneous SoC-FPGA platforms support multiple I/O cache coherence options between CPUs and FPGAs, but these options can have inadvertent effects on the achieved bandwidths depending on applications and data access patterns. To provide the most efficient communications between CPUs and accelerators, understanding the data transaction behaviors and selecting the right I/O cache coherence method is essential. In this work, we use Xilinx Zynq UltraScale+ with SDSoC and CUDA to quantitatively analyze the effect of using different I/O cache coherence schemes. Based on our analysis, we also explore possible software and hardware modifications in SoC-FPGA which can increase the overall acceleration performance by 20%.

 

Short bio: David Min is a PhD candidate working with Prof. Wen-mei Hwu in University of Illinois at Urbana-Champaign (UIUC). His primary interests are in computer architecture and high-bandwidth I/O designs. His current research projects include work on I/O cache coherence, near-memory acceleration, and OS kernel memory management. David is also a member of IBM’s Center for Cognitive Computing System Research (C3SR) and Application Driving Architecture (ADA) in Semiconductor Research Corporation (SRC)

Speakers

David Min is a PhD candidate working with Prof. Wen-mei Hwu in University of Illinois at Urbana-Champaign (UIUC).