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2011

Object Orienteed Execution Model (OOM)

2nd Workshop on New Directions in Computer Architecture (NDCA-2) Held in Conjunction with the 38th International Symposium on Computer Architecture (ISCA-38)

N. Markovic, D. Nemirovsky, R. González, O. Unsal, M. Valero, and A. Cristal
TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

Proc. FCCM '11

N. Sonmez, O. Arcas, O. Pflucker, O. Unsal, A. Cristal, I. Hur, S. Singh, and M. Valero
From Plasma to BeeFarm: Design Experience of an FPGA-based Multicore Prototype

ARC'11

N. Sonmez, O. Arcas, G. Sayilar, O. Unsal, A. Cristal, I. Hur, S. Singh, and M. Valero
{TMbox}: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

Proc. FCCM '11

N. Sonmez, O. Arcas, O. Pflucker, O. Unsal, A. Cristal, I. Hur, S. Singh, and M. Valero
Integrating dataflow abstractions into transactional memory

Systems for Future Multi-Core Architectures (SFMA'11)

V. Gajinov, A. Cristal, M. Milovanovic, E. Ayguade, O. Unsal, and M. Valero
True Vector Extensions for Decision Support DBMS Acceleration

T. Hayes, O. Palomar, O. Unsal, A. Cristal, and M. Valero
FaulTM-multi: Fault Tolerance for Multithreaded Applications Running on Transactional Memory Hardware

Workshop on Wild and Sane Ideas in Speculation and Transactions

G. Yalcin, O. Unsal, A. Cristal, and M. Valero
FIMSIM: A fault injection infrastructure for microarchitectural simulators

29th International Conference on Computer Design (ICCD)

G. Yalcin, O. Unsal, A. Cristal, and M. Valero
SymptomTM: Symptom Based Error Detection and Recovery Using Hardware Transactional Memory

Parallel Architectures and Compilation Techniques (PACT)

G. Yalcin, O. Unsal, A. Cristal, I. Hur, and M. Valero
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory

Parallel Architectures and Compilation Techniques (PACT)

A. Armejach, A. Seyedi, R T. J. Gil, I. Hur, O. Unsal, A. Cristal, and M. Valero

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