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2008

A distributed processor state management architecture for large-window processors

41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41)

I. González, M. Galluzzi, A. Veidenbaum, A. Ramirez, A. Cristal, and M. Valero
A Distributed Processor State Management Architecture for Large-Window Processors

I. González, M. Galluzzi, A. Veidenbaum, M. A. Ramírez, A. Cristal, and M. Valero
A distributed processor state management architecture for large-window processors

41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41)

I. González, M. Galluzzi, A. Veidenbaum, M. A. Ramírez, A. Cristal, and M. Valero
A Two-Level Load/Store Queue Based on Execution Locality

The 35th International Symposium on Computer Architecture (ISCA 2008)

M. Pericas, A. Cristal, F. Cazorla, R. González, A. Veidenbaum, D. A. Jiménez, and M. Valero

2005

A New Pointer-based Instruction Queue Design and Its Power-Performance Evaluation

IEEE International Conference on Computer Design (ICCD-2005)

M. A. Ramírez, A. Cristal, M. Valero, A. Veidenbaum, and L. A. Villa
Arquitectura Simétrica Clusterizada basada en el Contenido

XVI Jornadas de Paralelismo

R. González, A. Cristal, M. Pericas, A. Veidenbaum, and M. Valero
An asymetric Clustered Processor Based on Value Content

The 19th ACM International Conference on Supercomputing (ICS'05)

R. González, A. Cristal, M. Pericas, M. Valero, and A. Veidenbaum

2004

Banked Front-End Register File

M. Pericas, R. González, A. Cristal, A. Veidenbaum, and M. Valero
A clustered Processor based on Content-Aware Register File

R. González, A. Cristal, A. Veidenbaum, M. Pericas, and M. Valero
INSTRUCTION WAKEUP MECHANISM: Power and Timing Evaluation

CIC,s Research and Computing Science

M. A. Ramírez, A. Cristal, L. A. Villa, A. Veidenbaum, and M. Valero

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