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2010

An Asymmetric Distributed Shared Memory Model for Heterogeneous Parallel Systems

ACM SIGARCH Computer Architecture News - ASPLOS '10

I. Gelado, J. E. Stone, J. Cabezas, S. Patel, N. Navarro, and W-mei. Hwu
Decomposable and Responsive Power Models for Multicore Processors using Performance Counters

R. Bertran, M. González, X. Martorell, N. Navarro, and E. Ayguade

2009

High-Performance Reverse Time Migration on GPU

XXVIII International Conference of the Chilean Computer Society - XIII Workshop on Parallel and Distributed Systems (WSDP)

J. Cabezas, M. Araya-Polo, I. Gelado, N. Navarro, and J M.. Cela
Predictive Runtime Code Scheduling for Heterogeneous Architectures

V. J. Jiménez, L. Vilanova, I. Gelado, M. Gil, G. Fursin, and N. Navarro

2008

CUBA: an Architecture for Efficient CPU/co-processor Data Communication

22nd International Conference on Supercomputing

I. Gelado, J. H. Kelm, S. Ryoo, S. S. Lumetta, N. Navarro, and W-mei. Hwu
On-Chip memories, the OS perspective

5th HiPEAC Industrial Workshop

C. Villavieja, I. Gelado, A. Ramirez, and N. Navarro
Memory Management on Chip-MultiProcessors with on-chip Memories

Workshop on the Interaction between Operating Systems and Computer Architecture (WIOSCA'08)

I. Gelado, A. Ramirez, N. Navarro, and C. Villavieja

2007

High Performance Embedded Architectures and Compilation Roadmap

K D. Bosschere, W. Luk, X. Martorell, N. Navarro, M. O'Boyle, D. Pnevmatikatos, A. Ramirez, P. Sainrat, A. Seznec, P. Stenström, and O. Temam

2001

Strategies for Efficient Exploitation of Loop-Level Parallelism in Java Concurrency and Computation

Concurrency and Computation: Practice and Experience

J. Oliver, J. Guitart, E. Ayguade, N. Navarro, and J. Torres

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